don't expose reserved fields (bit ranges actually)

fixes #42

Author: Jorge Aparicio

ci/run.sh

@@ -19,6 +19,10 @@ test_mode() {
          https://raw.githubusercontent.com/posborne/cmsis-svd/python-0.4/data/Nordic/nrf51.svd \
          > $td/nrf51.svd
 
+    curl -L \
+         https://raw.githubusercontent.com/posborne/cmsis-svd/python-0.4/data/NXP/LPC43xx_svd_v5.svd \
+         > $td/LPC43xx_svd_v5.svd
+
     # test the library
     cargo build $flags
     cargo build $flags --release
@@ -36,10 +40,16 @@ test_mode() {
     test_gen tim3
     test_gen tim6
 
+    # Test register arrays
     svd=nrf51.svd
     test_gen
     test_gen gpio
     test_gen timer
+
+    # japaric/svd2rust#42
+    svd=LPC43xx_svd_v5.svd
+    test_gen
+    test_gen sct
 }
 
 deploy_mode() {

src/lib.rs

@@ -632,6 +632,12 @@ pub fn gen_register_r(r: &Register,
     let mut impl_items = vec![];
 
     for field in fields {
+        // Skip fields named RESERVED because, well, they are reserved so they
+        // shouldn't be modified/exposed
+        if field.name.to_lowercase() == "reserved" {
+            continue;
+        }
+
         if let Some(Access::WriteOnly) = field.access {
             continue;
         }
@@ -726,6 +732,11 @@ pub fn gen_register_w(r: &Register,
     }
 
     for field in fields {
+        // Skip fields named RESERVED. See `gen_register_r` for an explanation
+        if field.name.to_lowercase() == "reserved" {
+            continue;
+        }
+
         if let Some(Access::ReadOnly) = field.access {
             continue;
         }