Merge branch 'rust-embedded:master' into master

Author: romancardenas

svd-parser/CHANGELOG.md

@@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add `riscv` element for configuration parameters related to RISC-V targets.
   You must use the `unstable-riscv` feature to enable this exeperimental element.
 - Bump MSRV to 1.65.0
+- Bump roxmltree to 0.20
 
 ## [v0.14.5] - 2024-01-03
 

svd-parser/Cargo.toml

@@ -21,7 +21,7 @@ unstable-riscv = ["svd-rs/unstable-riscv"]
 
 [dependencies]
 svd-rs = { version = "0.14.7", path = "../svd-rs" }
-roxmltree = "0.19"
+roxmltree = "0.20"
 anyhow = "1.0.58"
 thiserror = "1.0.31"
 

svd-rs/CHANGELOG.md

@@ -11,6 +11,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add `riscv` element for configuration parameters related to RISC-V targets.
   You must use the `unstable-riscv` feature to enable this exeperimental element.
 - Add `DataType`
+- Fix run-time panic for write constraint check
 
 ## [v0.14.8] - 2024-02-13
 

svd-rs/src/field.rs

@@ -336,8 +336,13 @@ impl FieldInfo {
                 }
             }
 
-            if let Some(WriteConstraint::Range(constraint)) = self.write_constraint {
-                constraint.check_range(0..2_u64.pow(self.bit_range.width))?;
+            match self.write_constraint {
+                // If the bit_range has its maximum width, all values will of
+                // course fit in so we can skip validation.
+                Some(WriteConstraint::Range(constraint)) if self.bit_range.width < 64 => {
+                    constraint.check_range(0..2_u64.pow(self.bit_range.width))?;
+                }
+                _ => (),
             }
         }
 

tests/Cargo.toml

@@ -14,6 +14,6 @@ unstable-riscv = ["svd-rs/unstable-riscv", "svd-parser/unstable-riscv", "svd-enc
 svd-rs = { path = "../svd-rs"}
 svd-parser = { path = "../svd-parser"}
 svd-encoder = { path = "../svd-encoder"}
-roxmltree = "0.19"
+roxmltree = "0.20"
 xmltree = "0.10.3"
 anyhow = "1.0.45"