From 9e6a4d0396eebcdfaf1b80ea4042b5ebd792ec7e Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Sat, 8 Nov 2025 17:35:59 +0530 Subject: [PATCH 1/3] Implement DPC CSR for RISC-V --- riscv/CHANGELOG.md | 1 + riscv/src/register.rs | 1 + riscv/src/register/dpc.rs | 25 +++++++++++++++++++++++++ 3 files changed, 27 insertions(+) create mode 100644 riscv/src/register/dpc.rs diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md index 632e6e87..6e2471db 100644 --- a/riscv/CHANGELOG.md +++ b/riscv/CHANGELOG.md @@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/). ### Added +- Add `dpc` CSR support for RISC-V - Add Mtopi - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V - Add `miselect` CSR diff --git a/riscv/src/register.rs b/riscv/src/register.rs index 08c0f1a8..4655facb 100644 --- a/riscv/src/register.rs +++ b/riscv/src/register.rs @@ -131,3 +131,4 @@ mod tests; // TODO: Debug Mode Registers pub mod dcsr; +pub mod dpc; diff --git a/riscv/src/register/dpc.rs b/riscv/src/register/dpc.rs new file mode 100644 index 00000000..501814f8 --- /dev/null +++ b/riscv/src/register/dpc.rs @@ -0,0 +1,25 @@ +//! dpc register — Debug PC (0x7b1) + +read_write_csr! { + /// Debug PC Register + Dpc: 0x7b1, + mask: !1usize, +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn test_dpc_alignment_mask() { + let dpc = Dpc::from_bits(0x1); + assert_eq!(dpc.bits() & 1, 0); + } + + #[test] + fn test_dpc_bits_roundtrip() { + let dpc = Dpc::from_bits(0x12345); + assert_eq!(dpc.bits(), 0x12344); + assert_eq!(Dpc::from_bits(dpc.bits()).bits(), dpc.bits()); + } +} From 34f2498d5fe460911d7703dd2c77c64057a00cb9 Mon Sep 17 00:00:00 2001 From: Kushal Meghani <168952248+KushalMeghani1644@users.noreply.github.com> Date: Mon, 10 Nov 2025 16:21:40 +0530 Subject: [PATCH 2/3] Update riscv/src/register/dpc.rs Co-authored-by: rmsyn <117854522+rmsyn@users.noreply.github.com> --- riscv/src/register/dpc.rs | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/riscv/src/register/dpc.rs b/riscv/src/register/dpc.rs index 501814f8..f254dec8 100644 --- a/riscv/src/register/dpc.rs +++ b/riscv/src/register/dpc.rs @@ -18,8 +18,12 @@ mod tests { #[test] fn test_dpc_bits_roundtrip() { - let dpc = Dpc::from_bits(0x12345); - assert_eq!(dpc.bits(), 0x12344); - assert_eq!(Dpc::from_bits(dpc.bits()).bits(), dpc.bits()); + (0..=usize::BITS).map(|r| ((1u128 << r) - 1) as usize).for_each(|pc| { + // ensure lowest bit is cleared + let exp_pc = pc & !1usize; + let dpc = Dpc::from_bits(pc); + assert_eq!(dpc.bits(), exp_pc); + assert_eq!(Dpc::from_bits(dpc.bits()).bits(), dpc.bits()); + }); } } From f41190ebc235b15092927d52ebee19b6c9a0327c Mon Sep 17 00:00:00 2001 From: KushalMeghani1644 Date: Mon, 10 Nov 2025 16:42:04 +0530 Subject: [PATCH 3/3] Fix formatting --- riscv/src/register/dpc.rs | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/riscv/src/register/dpc.rs b/riscv/src/register/dpc.rs index f254dec8..b797be02 100644 --- a/riscv/src/register/dpc.rs +++ b/riscv/src/register/dpc.rs @@ -18,12 +18,14 @@ mod tests { #[test] fn test_dpc_bits_roundtrip() { - (0..=usize::BITS).map(|r| ((1u128 << r) - 1) as usize).for_each(|pc| { - // ensure lowest bit is cleared - let exp_pc = pc & !1usize; - let dpc = Dpc::from_bits(pc); - assert_eq!(dpc.bits(), exp_pc); - assert_eq!(Dpc::from_bits(dpc.bits()).bits(), dpc.bits()); - }); + (0..=usize::BITS) + .map(|r| ((1u128 << r) - 1) as usize) + .for_each(|pc| { + // ensure lowest bit is cleared + let exp_pc = pc & !1usize; + let dpc = Dpc::from_bits(pc); + assert_eq!(dpc.bits(), exp_pc); + assert_eq!(Dpc::from_bits(dpc.bits()).bits(), dpc.bits()); + }); } }