diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index 632e6e87..6e2471db 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
+- Add `dpc` CSR support for RISC-V
 - Add Mtopi
 - Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
 - Add `miselect` CSR
diff --git a/riscv/src/register.rs b/riscv/src/register.rs
index 08c0f1a8..4655facb 100644
--- a/riscv/src/register.rs
+++ b/riscv/src/register.rs
@@ -131,3 +131,4 @@ mod tests;
 
 // TODO: Debug Mode Registers
 pub mod dcsr;
+pub mod dpc;
diff --git a/riscv/src/register/dpc.rs b/riscv/src/register/dpc.rs
new file mode 100644
index 00000000..b797be02
--- /dev/null
+++ b/riscv/src/register/dpc.rs
@@ -0,0 +1,31 @@
+//! dpc register — Debug PC (0x7b1)
+
+read_write_csr! {
+    /// Debug PC Register
+    Dpc: 0x7b1,
+    mask: !1usize,
+}
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_dpc_alignment_mask() {
+        let dpc = Dpc::from_bits(0x1);
+        assert_eq!(dpc.bits() & 1, 0);
+    }
+
+    #[test]
+    fn test_dpc_bits_roundtrip() {
+        (0..=usize::BITS)
+            .map(|r| ((1u128 << r) - 1) as usize)
+            .for_each(|pc| {
+                // ensure lowest bit is cleared
+                let exp_pc = pc & !1usize;
+                let dpc = Dpc::from_bits(pc);
+                assert_eq!(dpc.bits(), exp_pc);
+                assert_eq!(Dpc::from_bits(dpc.bits()).bits(), dpc.bits());
+            });
+    }
+}