riscv: add mseccfgh unit tests

Adds basic unit tests for the `mseccfgh` CSR register.

Author: rmsyn

riscv/CHANGELOG.md

@@ -19,6 +19,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - New `riscv::register::xip::clear_pending` atomic function for `mip` and `sip` registers.
   This function is marked as `unsafe`, as its availability depends both on the target chip
   and the target interrupt source.
+- Add `mseccfg` CSR
+- Add `mseccfgh` CSR
 
 ### Changed
 

riscv/src/register/mseccfgh.rs

@@ -18,3 +18,17 @@ read_write_csr_field! {
     pmm,
     PMM: [0:1],
 }
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mseccfgh() {
+        let mut mseccfgh = Mseccfgh::from_bits(0);
+
+        test_csr_field!(mseccfgh, pmm: PMM::Disabled);
+        test_csr_field!(mseccfgh, pmm: PMM::EnabledXlen57);
+        test_csr_field!(mseccfgh, pmm: PMM::EnabledXlen48);
+    }
+}