Fix CHANGELOG.md

Author: KushalMeghani1644

riscv/CHANGELOG.md

@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## [v0.15.0] - 2025-09-08
 
 ### Added
+
 - New convenience  `try_new` and `new` associated functions for `Mtvec` and `Stvec`.
 - New methods and functions for enabling core interrupts in the `mie` and `sie` registers
   using the `riscv_pac::CoreInterruptNumber` trait.
@@ -116,7 +117,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   the CSR
 - Export `riscv::register::macros` module macros for external use
 - Add `riscv::register::mcountinhibit` module for `mcountinhibit` CSR
-- Add `Mcounteren` in-memory update functions 
+- Add `Mcounteren` in-memory update functions
 - Add `Mstatus` vector extension support
 - Add fallible counterparts to all functions that `panic`
 - Add `riscv-pac` as a dependency
@@ -285,4 +286,4 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
 [v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
 [v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5
-[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5u
+[v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5u