Merge #59

59: Release v0.7.1 r=Disasm a=khrs



Co-authored-by: Karol Harasim <karol.harasim@gmail.com>

Author: bors[bot]

riscv-rt/CHANGELOG.md

@@ -7,10 +7,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.7.1] - 2020-06-02
+
 ### Added
 
 - Add support to initialize custom interrupt controllers.
 
+### Changed
+
+ - Exception handler may return now
+
 ## [v0.7.0] - 2020-03-10
 
 ### Added
@@ -31,5 +37,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.0...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...HEAD
+[v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
 [v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0

riscv-rt/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.7.0"
+version = "0.7.1"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]