Adapt riscv-peripheral to edition 2024

Author: romancardenas

.github/workflows/riscv-peripheral.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.75.0
-        toolchain: [ stable, nightly, 1.75.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

riscv-peripheral/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Changed
+
+- Update to Rust edition 2024 (MSRV 1.85)
+
 ## [v0.3.0] - 2025-06-10
 
 ### Changed

riscv-peripheral/Cargo.toml

@@ -1,8 +1,8 @@
 [package]
 name = "riscv-peripheral"
 version = "0.3.0"
-edition = "2021"
-rust-version = "1.75"
+edition = "2024"
+rust-version = "1.85"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]

riscv-peripheral/README.md

@@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.75 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't**
 compile with older versions but that may change in any new patch release.
 
 ## License

riscv-peripheral/src/aclint.rs

@@ -78,8 +78,10 @@ impl<C: Clint> CLINT<C> {
     /// Enabling the `CLINT` may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        self.mswi().enable();
-        self.mtimer().enable();
+        unsafe {
+            self.mswi().enable();
+            self.mtimer().enable();
+        }
     }
 
     /// Disables machine timer **AND** software interrupts to prevent the CLINT from triggering interrupts.

riscv-peripheral/src/aclint/mswi.rs

@@ -64,7 +64,7 @@ impl<M: Mswi> MSWI<M> {
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        mie::set_msoft();
+        unsafe { mie::set_msoft() };
     }
 
     /// Disables machine software interrupts in the current HART.

riscv-peripheral/src/aclint/mtimer.rs

@@ -81,7 +81,7 @@ impl<M: Mtimer> MTIMER<M> {
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        mie::set_mtimer();
+        unsafe { mie::set_mtimer() };
     }
 
     /// Disables machine timer interrupts in the current HART.

riscv-peripheral/src/aclint/sswi.rs

@@ -55,7 +55,7 @@ impl<S: Sswi> SSWI<S> {
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        sie::set_ssoft();
+        unsafe { sie::set_ssoft() };
     }
 
     /// Disables supervisor software interrupts in the current HART.

riscv-peripheral/src/common.rs

@@ -265,7 +265,7 @@ macro_rules! peripheral {
             #[inline]
             pub const unsafe fn new(address: usize) -> Self {
                 Self {
-                    register: $crate::common::Reg::new(address as _),
+                    register: unsafe { $crate::common::Reg::new(address as _) },
                 }
             }
         }

riscv-peripheral/src/plic.rs

@@ -72,7 +72,7 @@ impl<P: Plic> PLIC<P> {
     /// Enabling the `PLIC` may break mask-based critical sections.
     #[inline]
     pub unsafe fn enable(self) {
-        mie::set_mext();
+        unsafe { mie::set_mext() };
     }
 
     /// Disables machine external interrupts to prevent the PLIC from triggering interrupts.