Use self instead of &self for consistency

Author: romancardenas

riscv-peripheral/src/aclint.rs

@@ -49,25 +49,25 @@ impl<C: Clint> CLINT<C> {
 
     /// Returns the [`MSWI`](mswi::MSWI) device.
     #[inline]
-    pub const fn mswi(&self) -> mswi::MSWI<C> {
+    pub const fn mswi(self) -> mswi::MSWI<C> {
         mswi::MSWI::new()
     }
 
     /// Returns the [`MTIMER`](mtimer::MTIMER) device.
     #[inline]
-    pub const fn mtimer(&self) -> mtimer::MTIMER<C> {
+    pub const fn mtimer(self) -> mtimer::MTIMER<C> {
         mtimer::MTIMER::new()
     }
 
     /// Returns `true` if a machine timer **OR** software interrupt is pending.
     #[inline]
-    pub fn is_interrupting(&self) -> bool {
+    pub fn is_interrupting(self) -> bool {
         self.mswi().is_interrupting() || self.mtimer().is_interrupting()
     }
 
     /// Returns `true` if machine timer **OR** software interrupts are enabled.
     #[inline]
-    pub fn is_enabled(&self) -> bool {
+    pub fn is_enabled(self) -> bool {
         self.mswi().is_enabled() || self.mtimer().is_enabled()
     }
 
@@ -77,14 +77,14 @@ impl<C: Clint> CLINT<C> {
     ///
     /// Enabling the `CLINT` may break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable(&self) {
+    pub unsafe fn enable(self) {
         self.mswi().enable();
         self.mtimer().enable();
     }
 
     /// Disables machine timer **AND** software interrupts to prevent the CLINT from triggering interrupts.
     #[inline]
-    pub fn disable(&self) {
+    pub fn disable(self) {
         self.mswi().disable();
         self.mtimer().disable();
     }

riscv-peripheral/src/aclint/mswi.rs

@@ -41,19 +41,19 @@ impl<M: Mswi> MSWI<M> {
 
     /// Returns the base address of the `MSWI` device.
     #[inline]
-    const fn as_ptr(&self) -> *const u32 {
+    const fn as_ptr(self) -> *const u32 {
         M::BASE as *const u32
     }
 
     /// Returns `true` if a machine software interrupt is pending.
     #[inline]
-    pub fn is_interrupting(&self) -> bool {
+    pub fn is_interrupting(self) -> bool {
         mip::read().msoft()
     }
 
     /// Returns `true` if machine software interrupts are enabled.
     #[inline]
-    pub fn is_enabled(&self) -> bool {
+    pub fn is_enabled(self) -> bool {
         mie::read().msoft()
     }
 
@@ -63,20 +63,20 @@ impl<M: Mswi> MSWI<M> {
     ///
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable(&self) {
+    pub unsafe fn enable(self) {
         mie::set_msoft();
     }
 
     /// Disables machine software interrupts in the current HART.
     #[inline]
-    pub fn disable(&self) {
+    pub fn disable(self) {
         // SAFETY: it is safe to disable interrupts
         unsafe { mie::clear_msoft() };
     }
 
     /// Returns the `MSIP` register for the HART which ID is `hart_id`.
     #[inline]
-    pub fn msip<H: HartIdNumber>(&self, hart_id: H) -> MSIP {
+    pub fn msip<H: HartIdNumber>(self, hart_id: H) -> MSIP {
         // SAFETY: `hart_id` is valid for the target
         unsafe { MSIP::new(self.as_ptr().add(hart_id.number()) as _) }
     }
@@ -88,7 +88,7 @@ impl<M: Mswi> MSWI<M> {
     /// This function determines the current HART ID by reading the `mhartid` CSR.
     /// Thus, it can only be used in M-mode. For S-mode, use [`MSWI::msip`] instead.
     #[inline]
-    pub fn msip_mhartid(&self) -> MSIP {
+    pub fn msip_mhartid(self) -> MSIP {
         let hart_id = mhartid::read();
         // SAFETY: `hart_id` is valid for the target and is the current hart
         unsafe { MSIP::new(self.as_ptr().add(hart_id) as _) }

riscv-peripheral/src/aclint/mtimer.rs

@@ -52,19 +52,19 @@ impl<M: Mtimer> MTIMER<M> {
 
     /// Returns the base address of the `MTIMECMP` registers.
     #[inline]
-    const fn mtimecmp_as_ptr(&self) -> *const u64 {
+    const fn mtimecmp_as_ptr(self) -> *const u64 {
         M::MTIMECMP_BASE as *const u64
     }
 
     /// Returns `true` if a machine timer interrupt is pending.
     #[inline]
-    pub fn is_interrupting(&self) -> bool {
+    pub fn is_interrupting(self) -> bool {
         mip::read().mtimer()
     }
 
     /// Returns `true` if machine timer interrupts are enabled.
     #[inline]
-    pub fn is_enabled(&self) -> bool {
+    pub fn is_enabled(self) -> bool {
         mie::read().mtimer()
     }
 
@@ -74,27 +74,27 @@ impl<M: Mtimer> MTIMER<M> {
     ///
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable(&self) {
+    pub unsafe fn enable(self) {
         mie::set_mtimer();
     }
 
     /// Disables machine timer interrupts in the current HART.
     #[inline]
-    pub fn disable(&self) {
+    pub fn disable(self) {
         // SAFETY: it is safe to disable interrupts
         unsafe { mie::clear_mtimer() };
     }
 
     /// Returns the `MTIME` register.
     #[inline]
-    pub const fn mtime(&self) -> MTIME {
+    pub const fn mtime(self) -> MTIME {
         // SAFETY: valid base address
         unsafe { MTIME::new(M::MTIME_BASE) }
     }
 
     /// Returns the `MTIMECMP` register for the HART which ID is `hart_id`.
     #[inline]
-    pub fn mtimecmp<H: HartIdNumber>(&self, hart_id: H) -> MTIMECMP {
+    pub fn mtimecmp<H: HartIdNumber>(self, hart_id: H) -> MTIMECMP {
         // SAFETY: `hart_id` is valid for the target
         unsafe { MTIMECMP::new(self.mtimecmp_as_ptr().add(hart_id.number()) as _) }
     }
@@ -106,7 +106,7 @@ impl<M: Mtimer> MTIMER<M> {
     /// This function determines the current HART ID by reading the [`mhartid`] CSR.
     /// Thus, it can only be used in M-mode. For S-mode, use [`MTIMER::mtimecmp`] instead.
     #[inline]
-    pub fn mtimecmp_mhartid(&self) -> MTIMECMP {
+    pub fn mtimecmp_mhartid(self) -> MTIMECMP {
         let hart_id = mhartid::read();
         // SAFETY: `hart_id` is valid for the target and is the current hart
         unsafe { MTIMECMP::new(self.mtimecmp_as_ptr().add(hart_id) as _) }

riscv-peripheral/src/aclint/sswi.rs

@@ -32,19 +32,19 @@ impl<S: Sswi> SSWI<S> {
 
     /// Returns the base address of the `SSWI` device.
     #[inline]
-    const fn as_ptr(&self) -> *const u32 {
+    const fn as_ptr(self) -> *const u32 {
         S::BASE as *const u32
     }
 
     /// Returns `true` if a supervisor software interrupt is pending.
     #[inline]
-    pub fn is_interrupting() -> bool {
+    pub fn is_interrupting(self) -> bool {
         sip::read().ssoft()
     }
 
     /// Returns `true` if supervisor software interrupts are enabled.
     #[inline]
-    pub fn is_enabled() -> bool {
+    pub fn is_enabled(self) -> bool {
         sie::read().ssoft()
     }
 
@@ -54,20 +54,20 @@ impl<S: Sswi> SSWI<S> {
     ///
     /// Enabling interrupts may break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable() {
+    pub unsafe fn enable(self) {
         sie::set_ssoft();
     }
 
     /// Disables supervisor software interrupts in the current HART.
     #[inline]
-    pub fn disable() {
+    pub fn disable(self) {
         // SAFETY: it is safe to disable interrupts
         unsafe { sie::clear_ssoft() };
     }
 
     /// Returns the `SETSSIP` register for the HART which ID is `hart_id`.
     #[inline]
-    pub fn setssip<H: HartIdNumber>(&self, hart_id: H) -> SETSSIP {
+    pub fn setssip<H: HartIdNumber>(self, hart_id: H) -> SETSSIP {
         // SAFETY: `hart_id` is valid for the target
         unsafe { SETSSIP::new(self.as_ptr().add(hart_id.number()) as _) }
     }

riscv-peripheral/src/plic.rs

@@ -55,13 +55,13 @@ impl<P: Plic> PLIC<P> {
 
     /// Returns `true` if a machine external interrupt is pending.
     #[inline]
-    pub fn is_interrupting(&self) -> bool {
+    pub fn is_interrupting(self) -> bool {
         mip::read().mext()
     }
 
     /// Returns true if machine external interrupts are enabled.
     #[inline]
-    pub fn is_enabled(&self) -> bool {
+    pub fn is_enabled(self) -> bool {
         mie::read().mext()
     }
 
@@ -71,13 +71,13 @@ impl<P: Plic> PLIC<P> {
     ///
     /// Enabling the `PLIC` may break mask-based critical sections.
     #[inline]
-    pub unsafe fn enable(&self) {
+    pub unsafe fn enable(self) {
         mie::set_mext();
     }
 
     /// Disables machine external interrupts to prevent the PLIC from triggering interrupts.
     #[inline]
-    pub fn disable(&self) {
+    pub fn disable(self) {
         // SAFETY: it is safe to disable interrupts
         unsafe { mie::clear_mext() };
     }
@@ -87,7 +87,7 @@ impl<P: Plic> PLIC<P> {
     /// This register allows to set the priority level of each interrupt source.
     /// The priority level of each interrupt source is shared among all the contexts.
     #[inline]
-    pub const fn priorities(&self) -> priorities::PRIORITIES {
+    pub const fn priorities(self) -> priorities::PRIORITIES {
         // SAFETY: valid address
         unsafe { priorities::PRIORITIES::new(P::BASE + Self::PRIORITIES_OFFSET) }
     }
@@ -96,14 +96,14 @@ impl<P: Plic> PLIC<P> {
     ///
     /// This register allows to check if a particular interrupt source is pending.
     #[inline]
-    pub const fn pendings(&self) -> pendings::PENDINGS {
+    pub const fn pendings(self) -> pendings::PENDINGS {
         // SAFETY: valid address
         unsafe { pendings::PENDINGS::new(P::BASE + Self::PENDINGS_OFFSET) }
     }
 
     /// Returns a proxy to access to all the PLIC registers of a given HART context.
     #[inline]
-    pub fn ctx<H: HartIdNumber>(&self, hart_id: H) -> CTX<P> {
+    pub fn ctx<H: HartIdNumber>(self, hart_id: H) -> CTX<P> {
         // SAFETY: valid context number
         unsafe { CTX::new(hart_id.number() as _) }
     }
@@ -115,7 +115,7 @@ impl<P: Plic> PLIC<P> {
     /// This function determines the current HART ID by reading the [`mhartid`] CSR.
     /// Thus, it can only be used in M-mode. For S-mode, use [`PLIC::ctx`] instead.
     #[inline]
-    pub fn ctx_mhartid(&self) -> CTX<P> {
+    pub fn ctx_mhartid(self) -> CTX<P> {
         let hart_id = mhartid::read();
         // SAFETY: `hart_id` is valid for the target and is the current hart
         unsafe { CTX::new(hart_id as _) }