register: add scontext register

Adds the definition for the `scontext` Supervisor debug context CSR.

Author: rmsyn

riscv/CHANGELOG.md

@@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - CSR helper macro `write_composite_csr` for writing 64-bit CSRs on 32-bit targets.
 - Write utilities for `mcycle`, `minstret`
 - Add `senvcfg` CSR
+- Add `scontext` CSR
 
 ### Changed
 

riscv/src/register.rs

@@ -57,6 +57,7 @@ pub mod stvec;
 
 // Supervisor Trap Handling
 pub mod scause;
+pub mod scontext;
 pub mod senvcfg;
 pub mod sepc;
 pub mod sip;

riscv/src/register/scontext.rs

@@ -0,0 +1,29 @@
+//! `scontext` register.
+
+#[cfg(target_arch = "riscv32")]
+const MASK: usize = 0xffff;
+#[cfg(not(target_arch = "riscv32"))]
+const MASK: usize = 0xffff_ffff;
+
+read_write_csr! {
+    /// `scontext` register.
+    Scontext: 0x5a8,
+    mask: MASK,
+}
+
+set!(0x5a8);
+clear!(0x5a8);
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Scontext,
+    /// Represents the `data` context number of the `scontext` CSR.
+    data: [0:15],
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Scontext,
+    /// Represents the `data` context number of the `scontext` CSR.
+    data: [0:31],
+}