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Merge pull request #246 from rust-embedded/asm
`riscv`: align assembly functions with `cortex-m`
2 parents b3a42fd + 2ba1abf commit 60800c1

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-73
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2 files changed

+70
-73
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‎riscv/CHANGELOG.md‎

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@@ -13,6 +13,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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### Changed
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- Align assembly functions with `cortex-m`
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- Use CSR helper macros to define `marchid` register
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- Re-use `try_*` functions in `mcountinhibit`
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- Use CSR helper macros to define `mcause` register

‎riscv/src/asm.rs‎

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@@ -1,30 +1,24 @@
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//! Assembly instructions
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macro_rules! instruction {
4-
($(#[$attr:meta])*, unsafe $fnname:ident, $asm:expr) => (
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($(#[$attr:meta])*, unsafe $fnname:ident, $asm:expr, $($options:tt)*) => (
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$(#[$attr])*
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#[inline]
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#[inline(always)]
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pub unsafe fn $fnname() {
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match () {
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#[cfg(riscv)]
10-
() => core::arch::asm!($asm),
11-
12-
#[cfg(not(riscv))]
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() => unimplemented!(),
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}
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
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core::arch::asm!($asm, $($options)*);
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#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
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unimplemented!();
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}
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);
17-
($(#[$attr:meta])*, $fnname:ident, $asm:expr) => (
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($(#[$attr:meta])*, $fnname:ident, $asm:expr, $($options:tt)*) => (
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$(#[$attr])*
19-
#[inline]
16+
#[inline(always)]
2017
pub fn $fnname() {
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match () {
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#[cfg(riscv)]
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() => unsafe { core::arch::asm!($asm) },
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#[cfg(not(riscv))]
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() => unimplemented!(),
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}
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#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
19+
unsafe { core::arch::asm!($asm, $($options)*) };
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#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
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unimplemented!();
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}
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);
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}
@@ -37,18 +31,35 @@ instruction!(
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///
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/// This function generates a no-operation; it's useful to prevent delay loops from being
3933
/// optimized away.
40-
, nop, "nop");
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, nop, "nop", options(nomem, nostack));
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instruction!(
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/// `WFI` instruction wrapper
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///
39+
/// Provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing.
40+
/// The WFI instruction is just a hint, and a legal implementation is to implement WFI as a NOP.
41+
, wfi, "wfi", options(nomem, nostack));
42+
4143
instruction!(
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/// `EBREAK` instruction wrapper
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///
4446
/// Generates a breakpoint exception.
45-
, unsafe ebreak, "ebreak");
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, unsafe ebreak, "ebreak", options(nomem, nostack));
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4649
instruction!(
47-
/// `WFI` instruction wrapper
50+
/// `ECALL` instruction wrapper
4851
///
49-
/// Provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing.
50-
/// The WFI instruction is just a hint, and a legal implementation is to implement WFI as a NOP.
51-
, wfi, "wfi");
52+
/// Generates an exception for a service request to the execution environment.
53+
/// When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode
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/// exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception,
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/// respectively, and performs no other operation.
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///
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/// # Note
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///
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/// The ECALL instruction will **NOT** save and restore the stack pointer, as it triggers an exception.
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/// The stack pointer must be saved and restored accordingly by the exception handler.
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, unsafe ecall, "ecall", options(nomem, nostack));
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instruction!(
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/// `SFENCE.VMA` instruction wrapper (all address spaces and page table levels)
5465
///
@@ -57,7 +68,8 @@ instruction!(
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/// are ordinarily not ordered with respect to loads and stores in the instruction stream.
5869
/// Executing an `SFENCE.VMA` instruction guarantees that any stores in the instruction stream prior to the
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/// `SFENCE.VMA` are ordered before all implicit references subsequent to the `SFENCE.VMA`.
60-
, sfence_vma_all, "sfence.vma");
71+
, sfence_vma_all, "sfence.vma", options(nostack));
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instruction!(
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/// `FENCE` instruction wrapper
6375
///
@@ -66,12 +78,12 @@ instruction!(
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/// (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination
6779
/// of the same. Informally, no other RISC-V hart or external device can observe any operation in the
6880
/// successor set following a FENCE before any operation in the predecessor set preceding the FENCE.
69-
/// Chapter 17 provides a precise description of the RISC-V memory consistency model.
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///
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/// The FENCE instruction also orders memory reads and writes made by the hart as observed by
7283
/// memory reads and writes made by an external device. However, FENCE does not order observations
7384
/// of events made by an external device using any other signaling mechanism.
74-
, fence, "fence");
85+
, fence, "fence", options(nostack));
86+
7587
instruction!(
7688
/// `FENCE.I` instruction wrapper
7789
///
@@ -89,7 +101,7 @@ instruction!(
89101
/// The unused fields in the FENCE.I instruction, imm\[11:0\], rs1, and rd, are reserved for
90102
/// finer-grain fences in future extensions. For forward compatibility, base
91103
/// implementations shall ignore these fields, and standard software shall zero these fields.
92-
, fence_i, "fence.i");
104+
, fence_i, "fence.i", options(nostack));
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94106
/// `SFENCE.VMA` instruction wrapper
95107
///
@@ -98,38 +110,18 @@ instruction!(
98110
/// are ordinarily not ordered with respect to loads and stores in the instruction stream.
99111
/// Executing an `SFENCE.VMA` instruction guarantees that any stores in the instruction stream prior to the
100112
/// `SFENCE.VMA` are ordered before all implicit references subsequent to the `SFENCE.VMA`.
101-
#[inline]
102-
#[allow(unused_variables)]
103-
pub unsafe fn sfence_vma(asid: usize, addr: usize) {
104-
match () {
105-
#[cfg(riscv)]
106-
() => core::arch::asm!("sfence.vma {0}, {1}", in(reg) addr, in(reg) asid),
107-
108-
#[cfg(not(riscv))]
109-
() => unimplemented!(),
110-
}
111-
}
112-
113-
/// `ECALL` instruction wrapper
114-
///
115-
/// Generates an exception for a service request to the execution environment.
116-
/// When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode
117-
/// exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception,
118-
/// respectively, and performs no other operation.
119-
///
120-
/// # Note
121-
///
122-
/// The ECALL instruction will **NOT** save and restore the stack pointer, as it triggers an exception.
123-
/// The stack pointer must be saved and restored accordingly by the exception handler.
124-
#[inline]
125-
pub unsafe fn ecall() {
126-
match () {
127-
#[cfg(riscv)]
128-
() => core::arch::asm!("ecall", options(nostack)),
129-
130-
#[cfg(not(riscv))]
131-
() => unimplemented!(),
132-
}
113+
#[inline(always)]
114+
#[cfg_attr(
115+
not(any(target_arch = "riscv32", target_arch = "riscv64")),
116+
allow(unused_variables)
117+
)]
118+
pub fn sfence_vma(asid: usize, addr: usize) {
119+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
120+
unsafe {
121+
core::arch::asm!("sfence.vma {0}, {1}", in(reg) addr, in(reg) asid, options(nostack));
122+
};
123+
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
124+
unimplemented!();
133125
}
134126

135127
/// Blocks the program for *at least* `cycles` CPU cycles.
@@ -142,22 +134,26 @@ pub unsafe fn ecall() {
142134
/// timer-less initialization of peripherals if and only if accurate timing is not essential. In
143135
/// any other case please use a more accurate method to produce a delay.
144136
#[inline]
145-
#[allow(unused_variables)]
137+
#[cfg_attr(
138+
not(any(target_arch = "riscv32", target_arch = "riscv64")),
139+
allow(unused_variables)
140+
)]
146141
pub fn delay(cycles: u32) {
147142
match () {
148-
#[cfg(riscv)]
149-
() => unsafe {
143+
#[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
144+
() => {
150145
let real_cyc = 1 + cycles / 2;
151-
core::arch::asm!(
152-
"2:",
153-
"addi {0}, {0}, -1",
154-
"bne {0}, zero, 2b",
155-
inout(reg) real_cyc => _,
156-
options(nomem, nostack),
157-
)
158-
},
159-
160-
#[cfg(not(riscv))]
146+
unsafe {
147+
core::arch::asm!(
148+
"2:",
149+
"addi {0}, {0}, -1",
150+
"bne {0}, zero, 2b",
151+
inout(reg) real_cyc => _,
152+
options(nomem, nostack),
153+
);
154+
}
155+
}
156+
#[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
161157
() => unimplemented!(),
162158
}
163159
}

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