register: add miselect CSR

Adds the `miselect` register for selecting an indirect CSR according to
the `Smcsrind` extension.

Reference:

<https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/isa_20240411/chapters/indirect-csr.html>

Author: 0xllx0

riscv/src/register.rs

@@ -117,6 +117,9 @@ pub mod mseccfg;
 #[cfg(any(test, target_arch = "riscv32"))]
 pub mod mseccfgh;
 
+// Machine indirect access
+pub mod miselect;
+
 #[cfg(test)]
 mod tests;
 

riscv/src/register/miselect.rs

@@ -0,0 +1,47 @@
+//! `miselect` register.
+
+const MASK: usize = usize::MAX;
+
+read_write_csr! {
+    /// `miselect` register.
+    Miselect: 0x350,
+    mask: MASK,
+}
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Miselect,
+    /// Returns whether `miselect` is for custom use of indirect CSRs.
+    is_custom: 31,
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Miselect,
+    /// Returns whether `miselect` is for custom use of indirect CSRs.
+    is_custom: 63,
+}
+
+#[cfg(target_arch = "riscv32")]
+read_write_csr_field! {
+    Miselect,
+    /// Gets the value stored in the `miselect` CSR.
+    ///
+    /// # Note
+    ///
+    /// The semantics of the value depend on the extension for the referenced CSR,
+    /// and the relevant `mireg*` value.
+    value: [0:30],
+}
+
+#[cfg(not(target_arch = "riscv32"))]
+read_write_csr_field! {
+    Miselect,
+    /// Gets the value stored in the `miselect` CSR.
+    ///
+    /// # Note
+    ///
+    /// The semantics of the value depend on the extension for the referenced CSR,
+    /// and the relevant `mireg*` value.
+    value: [0:62],
+}