riscv: bump MSRV to 1.67.0

Bumps the MSRV to 1.67.0 for the name change of the integer log
functions from `log` to `ilog` variants.

Author: rmsyn

.github/workflows/riscv-rt.yaml

@@ -10,8 +10,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.61.0
-        toolchain: [ stable, nightly, 1.61.0 ]
+        # All generated code should be running on stable now, MRSV is 1.67.0
+        toolchain: [ stable, nightly, 1.67.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32im-unknown-none-elf
@@ -28,9 +28,9 @@ jobs:
           - toolchain: nightly
             experimental: true
         exclude:
-          - toolchain: 1.61.0
+          - toolchain: 1.67.0
             target: riscv32im-unknown-none-elf
-          - toolchain: 1.61.0
+          - toolchain: 1.67.0
             target: riscv32imafc-unknown-none-elf
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}

.github/workflows/riscv-semihosting.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.61.0
-        toolchain: [ stable, nightly, 1.61.0 ]
+        # All generated code should be running on stable now, MRSV is 1.67.0
+        toolchain: [ stable, nightly, 1.67.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/riscv-target-parser.yaml

@@ -11,7 +11,7 @@ jobs:
     strategy:
       matrix:
         os: [ macos-latest, ubuntu-latest, windows-latest ]
-        toolchain: [ stable, nightly, 1.61.0 ]
+        toolchain: [ stable, nightly, 1.67.0 ]
         include:
           # Nightly is only for reference and allowed to fail
           - rust: nightly

.github/workflows/riscv.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.61.0
-        toolchain: [ stable, nightly, 1.61.0 ]
+        # All generated code should be running on stable now, MRSV is 1.67.0
+        toolchain: [ stable, nightly, 1.67.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/tests.yaml

@@ -20,8 +20,8 @@ jobs:
   run-build:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.61.0
-        toolchain: [ stable, nightly, 1.61.0 ]
+        # All generated code should be running on stable now, MRSV is 1.67.0
+        toolchain: [ stable, nightly, 1.67.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32im-unknown-none-elf
@@ -37,9 +37,9 @@ jobs:
           - toolchain: nightly
             experimental: true
         exclude:
-          - toolchain: 1.61.0
+          - toolchain: 1.67.0
             target: riscv32im-unknown-none-elf
-          - toolchain: 1.61.0
+          - toolchain: 1.67.0
             target: riscv32imafc-unknown-none-elf
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}

riscv/CHANGELOG.md

@@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Add `senvcfg` CSR
 - Add `scontext` CSR
 - Add `mconfigptr` CSR
+- Bump MSRV to 1.67.0 for `log` to `ilog` name change
 
 ### Changed
 

riscv/Cargo.toml

@@ -2,7 +2,7 @@
 name = "riscv"
 version = "0.13.0"
 edition = "2021"
-rust-version = "1.61"
+rust-version = "1.67"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]