Merge pull request #356 from rust-embedded/bump-msrv

Bump MSRV to 1.68

Author: MabezDev

.github/workflows/riscv-rt.yaml

@@ -10,8 +10,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.68.0
+        toolchain: [ stable, nightly, 1.68.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32im-unknown-none-elf
@@ -28,9 +28,9 @@ jobs:
           - toolchain: nightly
             experimental: true
         exclude:
-          - toolchain: 1.67.0
+          - toolchain: 1.68.0
             target: riscv32im-unknown-none-elf
-          - toolchain: 1.67.0
+          - toolchain: 1.68.0
             target: riscv32imafc-unknown-none-elf
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}

.github/workflows/riscv.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.68.0
+        toolchain: [ stable, nightly, 1.68.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

.github/workflows/tests.yaml

@@ -20,8 +20,8 @@ jobs:
   run-build:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.68.0
+        toolchain: [ stable, nightly, 1.68.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32im-unknown-none-elf
@@ -37,9 +37,9 @@ jobs:
           - toolchain: nightly
             experimental: true
         exclude:
-          - toolchain: 1.67.0
+          - toolchain: 1.68.0
             target: riscv32im-unknown-none-elf
-          - toolchain: 1.67.0
+          - toolchain: 1.68.0
             target: riscv32imafc-unknown-none-elf
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}

riscv-peripheral/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Fixed
+
+- Typo in documentation.
+
 ## [v0.4.0] - 2025-09-08
 
 ### Added

riscv-peripheral/src/aclint.rs

@@ -1,6 +1,6 @@
 //! Devices for the Core Local Interruptor (CLINT) and Advanced CLINT (ACLINT) peripherals.
 //!
-//! CLINT pecification: <https://github.com/pulp-platform/clint>
+//! CLINT specification: <https://github.com/pulp-platform/clint>
 //! ACLINT Specification: <https://github.com/riscvarchive/riscv-aclint/blob/main/riscv-aclint.adoc>
 
 pub mod mswi;

riscv-rt/CHANGELOG.md

@@ -9,6 +9,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Fix clippy warnings in riscv_rt_macros::strip_type_path
+- Bump MSRV to 1.68 for latest syn 2.0 release
 - Adapted to new `riscv` version.
 
 ## [v0.16.0] - 2025-09-08

riscv-rt/Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "riscv-rt"
 version = "0.16.0"
-rust-version = "1.67"
+rust-version = "1.68"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]

riscv-rt/macros/src/lib.rs

@@ -137,7 +137,7 @@ fn strip_type_path(ty: &Type) -> Option<Type> {
     match ty {
         Type::Ptr(ty) => {
             let mut ty = ty.clone();
-            ty.elem = Box::new(strip_type_path(&ty.elem)?);
+            *ty.elem = strip_type_path(&ty.elem)?;
             Some(Type::Ptr(ty))
         }
         Type::Path(ty) => {

riscv/CHANGELOG.md

@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 # Changed
 
+- Bump MSRV to 1.68 for latest version of syn 2.0
 - Now, `riscv::pac_enum` macro only includes trap-related code if `rt` or `rt-v-trap` features are enabled.
 
 ## [v0.15.0] - 2025-09-08

riscv/Cargo.toml

@@ -2,7 +2,7 @@
 name = "riscv"
 version = "0.15.0"
 edition = "2021"
-rust-version = "1.67"
+rust-version = "1.68"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]