Merge #63

63: Release v0.7.2 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>

Author: bors[bot]

riscv-rt/CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.7.2] - 2020-07-16
+
 ### Changed
 
 - Preserve `.eh_frame` and `.eh_frame_hdr` sections
@@ -42,6 +44,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Set MSRV to 1.38
 
 
-[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.1...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv-rt/compare/v0.7.2...HEAD
+[v0.7.2]: https://github.com/rust-embedded/riscv/compare/v0.7.1...v0.7.2
 [v0.7.1]: https://github.com/rust-embedded/riscv/compare/v0.7.0...v0.7.1
 [v0.7.0]: https://github.com/rust-embedded/riscv/compare/v0.6.1...v0.7.0

riscv-rt/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv-rt"
-version = "0.7.1"
+version = "0.7.2"
 repository = "https://github.com/rust-embedded/riscv-rt"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "no-std"]