fixup: riscv-peripheral: clippy fixes

Author: rmsyn

riscv-peripheral/CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+### Fixed
+
+- `clippy` fixes
+
 ## [v0.2.1] - 2025-02-18
 
 ### Changed

riscv-peripheral/src/aclint/mswi.rs

@@ -80,21 +80,23 @@ mod test {
     #[test]
     fn test_mswi() {
         // slice to emulate the interrupt pendings register
-        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER as usize + 1];
+        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER + 1];
         // SAFETY: valid memory address
         let mswi = unsafe { MSWI::new(raw_reg.as_ptr() as _) };
 
-        for i in 0..=HartId::MAX_HART_ID_NUMBER {
-            let hart_id = HartId::from_number(i).unwrap();
+        for (i, hart_id) in (0..raw_reg.len())
+            .map(|i| HartId::from_number(i).unwrap())
+            .enumerate()
+        {
             let msip = mswi.msip(hart_id);
             assert!(!msip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
             msip.pend();
             assert!(msip.is_pending());
-            assert_ne!(raw_reg[i as usize], 0);
+            assert_ne!(raw_reg[i], 0);
             msip.unpend();
             assert!(!msip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
         }
     }
 }

riscv-peripheral/src/aclint/mtimer.rs

@@ -66,7 +66,7 @@ mod test {
     #[test]
     fn check_mtimer() {
         // slice to emulate the mtimecmp registers
-        let raw_mtimecmp = [0u64; HartId::MAX_HART_ID_NUMBER as usize + 1];
+        let raw_mtimecmp = [0u64; HartId::MAX_HART_ID_NUMBER + 1];
         let raw_mtime = 0u64;
         // SAFETY: valid memory addresses
         let mtimer =

riscv-peripheral/src/aclint/sswi.rs

@@ -98,21 +98,23 @@ mod test {
     #[test]
     fn test_sswi() {
         // slice to emulate the interrupt pendings register
-        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER as usize + 1];
+        let raw_reg = [0u32; HartId::MAX_HART_ID_NUMBER + 1];
         // SAFETY: valid memory address
         let mswi = unsafe { SSWI::new(raw_reg.as_ptr() as _) };
 
-        for i in 0..=HartId::MAX_HART_ID_NUMBER {
-            let hart_id = HartId::from_number(i).unwrap();
+        for (i, hart_id) in (0..raw_reg.len())
+            .map(|i| HartId::from_number(i).unwrap())
+            .enumerate()
+        {
             let setssip = mswi.setssip(hart_id);
             assert!(!setssip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
             setssip.pend();
             assert!(setssip.is_pending());
-            assert_ne!(raw_reg[i as usize], 0);
+            assert_ne!(raw_reg[i], 0);
             setssip.unpend();
             assert!(!setssip.is_pending());
-            assert_eq!(raw_reg[i as usize], 0);
+            assert_eq!(raw_reg[i], 0);
         }
     }
 }

riscv-peripheral/src/plic.rs

@@ -292,7 +292,6 @@ pub(crate) mod test {
 
         for i in 0..=Context::MAX_HART_ID_NUMBER {
             let context = Context::from_number(i).unwrap();
-            let i = i as usize;
 
             let ctx = PLIC::ctx(context);