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lines changed Original file line number Diff line number Diff line change @@ -7,11 +7,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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88## [ Unreleased]
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10+ ### Changed
11+
12+ - Updated the license to ` MIT or Apache-2.0 `
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1014## [ v0.2.0] - 2024-10-19
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1216### Added
1317
14- - Updated the license to ` MIT or Apache-2.0 `
1518- Add ` result ` module for ` Error ` and ` Result ` types
1619- Add ` ExceptionNumber ` trait.
1720- Classify interrupt numbers in ` CoreInterruptNumber ` and ` ExternalInterruptNumber ` .
Original file line number Diff line number Diff line change @@ -9,14 +9,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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1010### Added
1111
12- - Updated the license to ` MIT or Apache-2.0 `
1312- Added DCSR (Debug Control and Status Register) CSR support for the RISC-V
1413- Add ` miselect ` CSR
1514- Improved assembly macro handling in asm.rs
1615- New ` rt ` and ` rt-v-trap ` features to opt-in ` riscv-rt ` -related code in ` riscv::pac_enum ` macro.
1716
1817# Changed
1918
19+ - Updated the license to ` MIT or Apache-2.0 `
2020- Bump MSRV to 1.68 for latest version of syn 2.0
2121- Now, ` riscv::pac_enum ` macro only includes trap-related code if ` rt ` or ` rt-v-trap ` features are enabled.
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