Update riscv/src/register/dcsr.rs

KushalMeghani1644 · romancardenas · web-flow · commit 02c1edf3f9eb · 2025-09-23T13:28:00.000+05:30
Co-authored-by: Román Cárdenas Rodríguez &lt;rcardenas.rod@gmail.com&gt;
diff --git a/riscv/src/register/dcsr.rs b/riscv/src/register/dcsr.rs
@@ -5,7 +5,7 @@
 read_write_csr! {
     /// Debug Control and Status Register
     Dcsr: 0x7b0,
-    mask: 0x8000_0fff,
+    mask: 0xf000_bfdf,
 }
 
 csr_field_enum! {

Original file line number	Diff line number	Diff line change
`@@ -5,7 +5,7 @@`
`5`	`5`	`read_write_csr! {`
`6`	`6`	`/// Debug Control and Status Register`
`7`	`7`	`Dcsr: 0x7b0,`
`8`		`- mask: 0x8000_0fff,`
	`8`	`+ mask: 0xf000_bfdf,`
`9`	`9`	`}`
`10`	`10`
`11`	`11`	`csr_field_enum! {`