11//! SPI bus sharing mechanisms.
22
3- use embedded_hal:: delay:: DelayUs ;
3+ use embedded_hal:: delay:: DelayNs ;
44use embedded_hal:: digital:: OutputPin ;
55use embedded_hal:: spi:: { ErrorType , Operation , SpiBus , SpiDevice } ;
66#[ cfg( feature = "async" ) ]
77use embedded_hal_async:: {
8- delay:: DelayUs as AsyncDelayUs ,
8+ delay:: DelayNs as AsyncDelayNs ,
99 spi:: { SpiBus as AsyncSpiBus , SpiDevice as AsyncSpiDevice } ,
1010} ;
1111
12+ use super :: shared:: transaction;
1213use super :: DeviceError ;
1314
1415/// [`SpiDevice`] implementation with exclusive access to the bus (not shared).
@@ -47,7 +48,7 @@ impl<BUS, CS> ExclusiveDevice<BUS, CS, super::NoDelay> {
4748 /// # Panics
4849 ///
4950 /// The returned device will panic if you try to execute a transaction
50- /// that contains any operations of type `Operation::DelayUs` .
51+ /// that contains any operations of type [ `Operation::DelayNs`] .
5152 #[ inline]
5253 pub fn new_no_delay ( bus : BUS , cs : CS ) -> Self {
5354 Self {
@@ -70,33 +71,11 @@ impl<Word: Copy + 'static, BUS, CS, D> SpiDevice<Word> for ExclusiveDevice<BUS,
7071where
7172 BUS : SpiBus < Word > ,
7273 CS : OutputPin ,
73- D : DelayUs ,
74+ D : DelayNs ,
7475{
7576 #[ inline]
7677 fn transaction ( & mut self , operations : & mut [ Operation < ' _ , Word > ] ) -> Result < ( ) , Self :: Error > {
77- self . cs . set_low ( ) . map_err ( DeviceError :: Cs ) ?;
78-
79- let op_res = operations. iter_mut ( ) . try_for_each ( |op| match op {
80- Operation :: Read ( buf) => self . bus . read ( buf) ,
81- Operation :: Write ( buf) => self . bus . write ( buf) ,
82- Operation :: Transfer ( read, write) => self . bus . transfer ( read, write) ,
83- Operation :: TransferInPlace ( buf) => self . bus . transfer_in_place ( buf) ,
84- Operation :: DelayUs ( us) => {
85- self . bus . flush ( ) ?;
86- self . delay . delay_us ( * us) ;
87- Ok ( ( ) )
88- }
89- } ) ;
90-
91- // On failure, it's important to still flush and deassert CS.
92- let flush_res = self . bus . flush ( ) ;
93- let cs_res = self . cs . set_high ( ) ;
94-
95- op_res. map_err ( DeviceError :: Spi ) ?;
96- flush_res. map_err ( DeviceError :: Spi ) ?;
97- cs_res. map_err ( DeviceError :: Cs ) ?;
98-
99- Ok ( ( ) )
78+ transaction ( operations, & mut self . bus , & mut self . delay , & mut self . cs )
10079 }
10180}
10281
@@ -106,7 +85,7 @@ impl<Word: Copy + 'static, BUS, CS, D> AsyncSpiDevice<Word> for ExclusiveDevice<
10685where
10786 BUS : AsyncSpiBus < Word > ,
10887 CS : OutputPin ,
109- D : AsyncDelayUs ,
88+ D : AsyncDelayNs ,
11089{
11190 #[ inline]
11291 async fn transaction (
@@ -122,10 +101,10 @@ where
122101 Operation :: Write ( buf) => self . bus . write ( buf) . await ,
123102 Operation :: Transfer ( read, write) => self . bus . transfer ( read, write) . await ,
124103 Operation :: TransferInPlace ( buf) => self . bus . transfer_in_place ( buf) . await ,
125- Operation :: DelayUs ( us ) => match self . bus . flush ( ) . await {
104+ Operation :: DelayNs ( ns ) => match self . bus . flush ( ) . await {
126105 Err ( e) => Err ( e) ,
127106 Ok ( ( ) ) => {
128- self . delay . delay_us ( * us ) . await ;
107+ self . delay . delay_ns ( * ns ) . await ;
129108 Ok ( ( ) )
130109 }
131110 } ,
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