cortex-m: fix typos

Author: newAM

cortex-m/src/interrupt.rs

@@ -54,7 +54,7 @@ pub unsafe fn enable() {
 
 /// Execute closure `f` with interrupts disabled in the current core.
 ///
-/// This method does not synchronise multiple cores and may disable required
+/// This method does not synchronize multiple cores and may disable required
 /// interrupts on some platforms; see the `critical-section` crate for a cross-platform
 /// way to enter a critical section which provides a `CriticalSection` token.
 ///

cortex-m/src/macros.rs

@@ -37,7 +37,7 @@ macro_rules! iprintln {
 /// have to provide one from elsewhere, typically your chip's HAL crate.
 ///
 /// For debuggability, you can set an explicit name for a singleton.  This name only shows up the
-/// the debugger and is not referencable from other code.  See example below.
+/// the debugger and is not referenceable from other code.  See example below.
 ///
 /// # Example
 ///

cortex-m/src/peripheral/ac.rs

@@ -16,7 +16,7 @@ pub struct RegisterBlock {
     /// AHB Slave Control Register
     pub ahbscr: RW<u32>,
     reserved0: u32,
-    /// Auxilary Bus Fault Status Register
+    /// Auxiliary Bus Fault Status Register
     pub abfsr: RW<u32>,
 }
 

cortex-m/src/peripheral/scb.rs

@@ -362,7 +362,7 @@ impl SCB {
         let mut cbp = unsafe { CBP::new() };
 
         // Disable I-cache
-        // NOTE(unsafe): We have synchronised access by &mut self
+        // NOTE(unsafe): We have synchronized access by &mut self
         unsafe { self.ccr.modify(|r| r & !SCB_CCR_IC_MASK) };
 
         // Invalidate I-cache
@@ -435,7 +435,7 @@ impl SCB {
         }
 
         // Turn off the D-cache
-        // NOTE(unsafe): We have synchronised access by &mut self
+        // NOTE(unsafe): We have synchronized access by &mut self
         unsafe { self.ccr.modify(|r| r & !SCB_CCR_DC_MASK) };
 
         // Clean and invalidate whatever was left in it