fix and cleanup offsets in nvic

Author: sphw

src/peripheral/nvic.rs

@@ -33,17 +33,18 @@ pub struct RegisterBlock {
     /// Interrupt Active Bit (not present on Cortex-M0 variants)
     #[cfg(not(armv6m))]
     pub iabr: [RO<u32>; 16],
-    #[cfg(any(armv6m, armv8m))]
+    #[cfg(armv6m)]
     _reserved4: [u32; 16],
 
+    _reserved5: [u32; 16],
+
     #[cfg(armv8m)]
     /// Interrupt Target Non-secure (only present on Arm v8-M)
     pub itns: [RW<u32>; 16],
-    #[cfg(armv8m)]
-    _reserved5: [u32; 32],
-
     #[cfg(not(armv8m))]
-    _reserved5: [u32; 48],
+    _reserved6: [u32; 16],
+
+    _reserved7: [u32; 16],
 
     /// Interrupt Priority
     ///
@@ -74,7 +75,7 @@ pub struct RegisterBlock {
     pub ipr: [RW<u32>; 8],
 
     #[cfg(not(armv6m))]
-    _reserved6: [u32; 580],
+    _reserved8: [u32; 580],
 
     /// Software Trigger Interrupt
     #[cfg(not(armv6m))]