Add #[inline] to lots of trivial functions.

Author: m-ou-se

src/itm.rs

@@ -21,6 +21,7 @@ unsafe fn write_words(stim: &mut Stim, bytes: &[u32]) {
 struct Port<'p>(&'p mut Stim);
 
 impl<'p> fmt::Write for Port<'p> {
+    #[inline]
     fn write_str(&mut self, s: &str) -> fmt::Result {
         write_all(self.0, s.as_bytes());
         Ok(())
@@ -126,13 +127,15 @@ pub fn write_aligned(port: &mut Stim, buffer: &Aligned<A4, [u8]>) {
 }
 
 /// Writes `fmt::Arguments` to the ITM `port`
+#[inline]
 pub fn write_fmt(port: &mut Stim, args: fmt::Arguments) {
     use core::fmt::Write;
 
     Port(port).write_fmt(args).ok();
 }
 
 /// Writes a string to the ITM `port`
+#[inline]
 pub fn write_str(port: &mut Stim, string: &str) {
     write_all(port, string.as_bytes())
 }

src/peripheral/cpuid.rs

@@ -82,6 +82,7 @@ impl CPUID {
     /// * `ind`: select instruction cache or data/unified cache
     ///
     /// `level` is masked to be between 0 and 7.
+    #[inline]
     pub fn select_cache(&mut self, level: u8, ind: CsselrCacheType) {
         const CSSELR_IND_POS: u32 = 0;
         const CSSELR_IND_MASK: u32 = 1 << CSSELR_IND_POS;
@@ -97,6 +98,7 @@ impl CPUID {
     }
 
     /// Returns the number of sets and ways in the selected cache
+    #[inline]
     pub fn cache_num_sets_ways(&mut self, level: u8, ind: CsselrCacheType) -> (u16, u16) {
         const CCSIDR_NUMSETS_POS: u32 = 13;
         const CCSIDR_NUMSETS_MASK: u32 = 0x7FFF << CCSIDR_NUMSETS_POS;

src/peripheral/dcb.rs

@@ -25,6 +25,7 @@ impl DCB {
     /// `peripheral::DWT` cycle counter to work properly.
     /// As by STM documentation, this flag is not reset on
     /// soft-reset, only on power reset.
+    #[inline]
     pub fn enable_trace(&mut self) {
         // set bit 24 / TRCENA
         unsafe {
@@ -33,6 +34,7 @@ impl DCB {
     }
 
     /// Disables TRACE. See `DCB::enable_trace()` for more details
+    #[inline]
     pub fn disable_trace(&mut self) {
         // unset bit 24 / TRCENA
         unsafe {
@@ -47,6 +49,7 @@ impl DCB {
     /// on Cortex-M0 devices. Per the ARM v6-M Architecture Reference Manual, "Access to the DHCSR
     /// from software running on the processor is IMPLEMENTATION DEFINED". Indeed, from the
     /// [Cortex-M0+ r0p1 Technical Reference Manual](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0484c/BABJHEIG.html), "Note Software cannot access the debug registers."
+    #[inline]
     pub fn is_debugger_attached() -> bool {
         unsafe {
             // do an 8-bit read of the 32-bit DHCSR register, and get the LSB

src/peripheral/dwt.rs

@@ -65,12 +65,14 @@ pub struct Comparator {
 impl DWT {
     /// Enables the cycle counter
     #[cfg(not(armv6m))]
+    #[inline]
     pub fn enable_cycle_counter(&mut self) {
         unsafe { self.ctrl.modify(|r| r | 1) }
     }
 
     /// Returns the current clock cycle count
     #[cfg(not(armv6m))]
+    #[inline]
     pub fn get_cycle_count() -> u32 {
         // NOTE(unsafe) atomic read with no side effects
         unsafe { (*Self::ptr()).cyccnt.read() }

src/peripheral/itm.rs

@@ -35,21 +35,25 @@ pub struct Stim {
 
 impl Stim {
     /// Writes an `u8` payload into the stimulus port
+    #[inline]
     pub fn write_u8(&mut self, value: u8) {
         unsafe { ptr::write_volatile(self.register.get() as *mut u8, value) }
     }
 
     /// Writes an `u16` payload into the stimulus port
+    #[inline]
     pub fn write_u16(&mut self, value: u16) {
         unsafe { ptr::write_volatile(self.register.get() as *mut u16, value) }
     }
 
     /// Writes an `u32` payload into the stimulus port
+    #[inline]
     pub fn write_u32(&mut self, value: u32) {
         unsafe { ptr::write_volatile(self.register.get(), value) }
     }
 
     /// Returns `true` if the stimulus port is ready to accept more data
+    #[inline]
     pub fn is_fifo_ready(&self) -> bool {
         unsafe { ptr::read_volatile(self.register.get()) == 1 }
     }

src/peripheral/mod.rs

@@ -158,6 +158,7 @@ impl Peripherals {
     }
 
     /// Unchecked version of `Peripherals::take`
+    #[inline]
     pub unsafe fn steal() -> Self {
         CORE_PERIPHERALS = true;
 
@@ -211,13 +212,15 @@ unsafe impl Send for CBP {}
 
 #[cfg(not(armv6m))]
 impl CBP {
+    #[inline(always)]
     pub(crate) unsafe fn new() -> Self {
         CBP {
             _marker: PhantomData,
         }
     }
 
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const self::cbp::RegisterBlock {
         0xE000_EF50 as *const _
     }
@@ -227,6 +230,7 @@ impl CBP {
 impl ops::Deref for CBP {
     type Target = self::cbp::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -241,6 +245,7 @@ unsafe impl Send for CPUID {}
 
 impl CPUID {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const self::cpuid::RegisterBlock {
         0xE000_ED00 as *const _
     }
@@ -249,6 +254,7 @@ impl CPUID {
 impl ops::Deref for CPUID {
     type Target = self::cpuid::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -263,6 +269,7 @@ unsafe impl Send for DCB {}
 
 impl DCB {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const dcb::RegisterBlock {
         0xE000_EDF0 as *const _
     }
@@ -271,6 +278,7 @@ impl DCB {
 impl ops::Deref for DCB {
     type Target = self::dcb::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*DCB::ptr() }
     }
@@ -285,6 +293,7 @@ unsafe impl Send for DWT {}
 
 impl DWT {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const dwt::RegisterBlock {
         0xE000_1000 as *const _
     }
@@ -293,6 +302,7 @@ impl DWT {
 impl ops::Deref for DWT {
     type Target = self::dwt::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -308,6 +318,7 @@ unsafe impl Send for FPB {}
 #[cfg(not(armv6m))]
 impl FPB {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const fpb::RegisterBlock {
         0xE000_2000 as *const _
     }
@@ -317,6 +328,7 @@ impl FPB {
 impl ops::Deref for FPB {
     type Target = self::fpb::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -332,6 +344,7 @@ unsafe impl Send for FPU {}
 #[cfg(any(has_fpu, target_arch = "x86_64"))]
 impl FPU {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const fpu::RegisterBlock {
         0xE000_EF30 as *const _
     }
@@ -341,6 +354,7 @@ impl FPU {
 impl ops::Deref for FPU {
     type Target = self::fpu::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -356,6 +370,7 @@ unsafe impl Send for ITM {}
 #[cfg(not(armv6m))]
 impl ITM {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *mut itm::RegisterBlock {
         0xE000_0000 as *mut _
     }
@@ -365,13 +380,15 @@ impl ITM {
 impl ops::Deref for ITM {
     type Target = self::itm::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
 }
 
 #[cfg(not(armv6m))]
 impl ops::DerefMut for ITM {
+    #[inline(always)]
     fn deref_mut(&mut self) -> &mut Self::Target {
         unsafe { &mut *Self::ptr() }
     }
@@ -386,6 +403,7 @@ unsafe impl Send for MPU {}
 
 impl MPU {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const mpu::RegisterBlock {
         0xE000_ED90 as *const _
     }
@@ -394,6 +412,7 @@ impl MPU {
 impl ops::Deref for MPU {
     type Target = self::mpu::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -408,6 +427,7 @@ unsafe impl Send for NVIC {}
 
 impl NVIC {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const nvic::RegisterBlock {
         0xE000_E100 as *const _
     }
@@ -416,6 +436,7 @@ impl NVIC {
 impl ops::Deref for NVIC {
     type Target = self::nvic::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -430,6 +451,7 @@ unsafe impl Send for SCB {}
 
 impl SCB {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const scb::RegisterBlock {
         0xE000_ED04 as *const _
     }
@@ -438,6 +460,7 @@ impl SCB {
 impl ops::Deref for SCB {
     type Target = self::scb::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -452,6 +475,7 @@ unsafe impl Send for SYST {}
 
 impl SYST {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const syst::RegisterBlock {
         0xE000_E010 as *const _
     }
@@ -460,6 +484,7 @@ impl SYST {
 impl ops::Deref for SYST {
     type Target = self::syst::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }
@@ -475,6 +500,7 @@ unsafe impl Send for TPIU {}
 #[cfg(not(armv6m))]
 impl TPIU {
     /// Returns a pointer to the register block
+    #[inline(always)]
     pub fn ptr() -> *const tpiu::RegisterBlock {
         0xE004_0000 as *const _
     }
@@ -484,6 +510,7 @@ impl TPIU {
 impl ops::Deref for TPIU {
     type Target = self::tpiu::RegisterBlock;
 
+    #[inline(always)]
     fn deref(&self) -> &Self::Target {
         unsafe { &*Self::ptr() }
     }