Merge pull request #29 from riscv-rust/v0_11_0

almindor · web-flow · commit 662320f26c59 · 2023-03-29T08:50:06.000-07:00
release v0.11.0
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -7,8 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.11.0]
+
 ### Changed
 - Update `riscv` dependency to version 0.10
+- Regenerate code with `svd2rust` v0.26.0
 
 ## [v0.10.0] - 2022-09-04
 
diff --git a/Cargo.toml b/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "e310x"
-version = "0.10.0"
+version = "0.11.0"
 repository = "https://github.com/riscv-rust/e310x"
 authors = ["David Craven <david@craven.ch>", "The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]
@@ -18,4 +18,4 @@ rt = []
 g002 = []
 
 [package.metadata.docs.rs]
-features = ["rt", "g002"]
+features = ["rt", "g002", "critical-section"]
diff --git a/device.x b/device.x
@@ -1,3 +1,8 @@
+MEMORY
+{
+    RAM : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
 PROVIDE(WATCHDOG = DefaultHandler);
 PROVIDE(RTC = DefaultHandler);
 PROVIDE(UART0 = DefaultHandler);
diff --git a/memory.x b/memory.x
@@ -0,0 +1,5 @@
+MEMORY
+{
+    RAM : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
diff --git a/update.sh b/update.sh
@@ -10,3 +10,8 @@ mv generic.rs src/
 form -i lib.rs -o src/
 rm lib.rs
 cargo fmt
+
+# combine generated device.x with memory.x
+mv device.x ints.x
+cat memory.x ints.x > device.x
+rm -f ints.x

-Original file line number
+Diff line change
@@ @@ -0,0 +1,5 @@ @@
 +MEMORY
 +{
 +    RAM : ORIGIN = 0x80000000, LENGTH = 16K
 +}
++