fix(examples): enforce 256-byte alignment on exception vector table for Cortex-M0+

yvt · yvt · commit 824e974a5ca3 · 2022-03-10T01:58:28.000+09:00
Cortex-M0+ Technical Reference Manual:

&gt; If implemented, the VTOR enables bits[31:8] of the vector table
&gt; address to be specified.

Fixes `smp_rp_pico` misbehaving depending on seemingly unknown factors.
diff --git a/examples/smp_rp_pico/src/core1.rs b/examples/smp_rp_pico/src/core1.rs
@@ -86,7 +86,9 @@ unsafe extern "C" fn core1_entry() -> ! {
     unsafe { <SystemTraits as port::EntryPoint>::start() }
 }
 
-#[repr(C, align(128))]
+// Cortex-M0+ Technical Reference Manual: “If implemented, the VTOR enables
+// bits[31:8] of the vector table address to be specified.”
+#[repr(C, align(256))]
 struct VectorTable<T>(T);
 
 static CORE1_VECTOR_TABLE: VectorTable<[unsafe extern "C" fn(); 48]> = {

Original file line number	Diff line number	Diff line change
`@@ -86,7 +86,9 @@ unsafe extern "C" fn core1_entry() -> ! {`
`86`	`86`	`unsafe { <SystemTraits as port::EntryPoint>::start() }`
`87`	`87`	`}`
`88`	`88`
`89`		`-#[repr(C, align(128))]`
	`89`	`+// Cortex-M0+ Technical Reference Manual: “If implemented, the VTOR enables`
	`90`	`+// bits[31:8] of the vector table address to be specified.”`
	`91`	`+#[repr(C, align(256))]`
`90`	`92`	`struct VectorTable<T>(T);`
`91`	`93`
`92`	`94`	`static CORE1_VECTOR_TABLE: VectorTable<[unsafe extern "C" fn(); 48]> = {`