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Merge pull request #287 from fbarchard/smelen
2 parents 39ea79a + 2cd6d6d commit b728a23

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+31
-2
lines changed

4 files changed

+31
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.github/workflows/build.yml

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@@ -94,14 +94,14 @@ jobs:
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env:
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ANDROID_NDK: ${{ steps.setup-ndk.outputs.ndk-path }}
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cmake-linux-qemu:
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runs-on: ubuntu-22.04
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runs-on: ubuntu-24.04
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timeout-minutes: 40
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strategy:
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matrix:
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build_props:
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- [
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"cmake-linux-riscv64",
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"riscv64/ubuntu:22.04"
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"riscv64/ubuntu:24.04"
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]
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name: ${{ matrix.build_props[0] }}

include/cpuinfo.h

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@@ -1700,6 +1700,7 @@ struct cpuinfo_arm_isa {
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bool sme_b16b16;
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bool sme_f16f16;
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uint32_t svelen;
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uint32_t smelen;
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#endif
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bool rdm;
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bool fp16arith;
@@ -2081,6 +2082,15 @@ static inline uint32_t cpuinfo_get_max_arm_sve_length(void) {
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#endif
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}
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// Function to get the max SME vector length on ARM CPU's which support SME.
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static inline uint32_t cpuinfo_get_max_arm_sme_length(void) {
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#if CPUINFO_ARCH_ARM64
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return cpuinfo_isa.smelen * 8; // bytes * 8 = bit length(vector length)
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#else
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return 0;
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#endif
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}
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static inline bool cpuinfo_has_arm_sme(void) {
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#if CPUINFO_ARCH_ARM64
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return cpuinfo_isa.sme;

src/arm/linux/aarch64-isa.c

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@@ -191,4 +191,22 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo(
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// Mask out the SVE vector length bits
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isa->svelen = ret & PR_SVE_VL_LEN_MASK;
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}
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#ifndef PR_SME_GET_VL
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#define PR_SME_GET_VL 64
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#endif
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#ifndef PR_SME_VL_LEN_MASK
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#define PR_SME_VL_LEN_MASK 0xffff
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#endif
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ret = prctl(PR_SME_GET_VL);
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if (ret < 0) {
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cpuinfo_log_warning("No SME support on this machine");
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isa->smelen = 0; // Assume no SME support if the call fails
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} else {
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// Mask out the SME vector length bits
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isa->smelen = ret & PR_SME_VL_LEN_MASK;
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}
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}
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tools/isa-info.c

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@@ -178,6 +178,7 @@ int main(int argc, char** argv) {
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printf("ARM SVE Capabilities:\n");
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printf("\tSVE max length: %d\n", cpuinfo_get_max_arm_sve_length());
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printf("\tSME max length: %d\n", cpuinfo_get_max_arm_sme_length());
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printf("Cryptography extensions:\n");
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printf("\tAES: %s\n", cpuinfo_has_arm_aes() ? "yes" : "no");

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