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author
Ozan Aydin
authored
- clang format
1 parent bf43522 commit 7bca5ef

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-275
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2 files changed

+267
-275
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‎src/arm/api.h‎

Lines changed: 87 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
#pragma once
22

33
#ifdef _MSC_VER
4-
#define RESTRICT_STATIC /* nothing for MSVC */
4+
#define RESTRICT_STATIC /* nothing for MSVC */
55
#else
6-
#define RESTRICT_STATIC restrict static
6+
#define RESTRICT_STATIC restrict static
77
#endif
88

99
#include <stdbool.h>
@@ -13,121 +13,112 @@
1313
#include <cpuinfo/common.h>
1414

1515
enum cpuinfo_arm_chipset_vendor {
16-
cpuinfo_arm_chipset_vendor_unknown = 0,
17-
cpuinfo_arm_chipset_vendor_qualcomm,
18-
cpuinfo_arm_chipset_vendor_mediatek,
19-
cpuinfo_arm_chipset_vendor_samsung,
20-
cpuinfo_arm_chipset_vendor_hisilicon,
21-
cpuinfo_arm_chipset_vendor_actions,
22-
cpuinfo_arm_chipset_vendor_allwinner,
23-
cpuinfo_arm_chipset_vendor_amlogic,
24-
cpuinfo_arm_chipset_vendor_broadcom,
25-
cpuinfo_arm_chipset_vendor_lg,
26-
cpuinfo_arm_chipset_vendor_leadcore,
27-
cpuinfo_arm_chipset_vendor_marvell,
28-
cpuinfo_arm_chipset_vendor_mstar,
29-
cpuinfo_arm_chipset_vendor_novathor,
30-
cpuinfo_arm_chipset_vendor_nvidia,
31-
cpuinfo_arm_chipset_vendor_pinecone,
32-
cpuinfo_arm_chipset_vendor_renesas,
33-
cpuinfo_arm_chipset_vendor_rockchip,
34-
cpuinfo_arm_chipset_vendor_spreadtrum,
35-
cpuinfo_arm_chipset_vendor_telechips,
36-
cpuinfo_arm_chipset_vendor_texas_instruments,
37-
cpuinfo_arm_chipset_vendor_unisoc,
38-
cpuinfo_arm_chipset_vendor_wondermedia,
39-
cpuinfo_arm_chipset_vendor_max,
16+
cpuinfo_arm_chipset_vendor_unknown = 0,
17+
cpuinfo_arm_chipset_vendor_qualcomm,
18+
cpuinfo_arm_chipset_vendor_mediatek,
19+
cpuinfo_arm_chipset_vendor_samsung,
20+
cpuinfo_arm_chipset_vendor_hisilicon,
21+
cpuinfo_arm_chipset_vendor_actions,
22+
cpuinfo_arm_chipset_vendor_allwinner,
23+
cpuinfo_arm_chipset_vendor_amlogic,
24+
cpuinfo_arm_chipset_vendor_broadcom,
25+
cpuinfo_arm_chipset_vendor_lg,
26+
cpuinfo_arm_chipset_vendor_leadcore,
27+
cpuinfo_arm_chipset_vendor_marvell,
28+
cpuinfo_arm_chipset_vendor_mstar,
29+
cpuinfo_arm_chipset_vendor_novathor,
30+
cpuinfo_arm_chipset_vendor_nvidia,
31+
cpuinfo_arm_chipset_vendor_pinecone,
32+
cpuinfo_arm_chipset_vendor_renesas,
33+
cpuinfo_arm_chipset_vendor_rockchip,
34+
cpuinfo_arm_chipset_vendor_spreadtrum,
35+
cpuinfo_arm_chipset_vendor_telechips,
36+
cpuinfo_arm_chipset_vendor_texas_instruments,
37+
cpuinfo_arm_chipset_vendor_unisoc,
38+
cpuinfo_arm_chipset_vendor_wondermedia,
39+
cpuinfo_arm_chipset_vendor_max,
4040
};
4141

4242
enum cpuinfo_arm_chipset_series {
43-
cpuinfo_arm_chipset_series_unknown = 0,
44-
cpuinfo_arm_chipset_series_qualcomm_qsd,
45-
cpuinfo_arm_chipset_series_qualcomm_msm,
46-
cpuinfo_arm_chipset_series_qualcomm_apq,
47-
cpuinfo_arm_chipset_series_qualcomm_snapdragon,
48-
cpuinfo_arm_chipset_series_mediatek_mt,
49-
cpuinfo_arm_chipset_series_samsung_exynos,
50-
cpuinfo_arm_chipset_series_hisilicon_k3v,
51-
cpuinfo_arm_chipset_series_hisilicon_hi,
52-
cpuinfo_arm_chipset_series_hisilicon_kirin,
53-
cpuinfo_arm_chipset_series_actions_atm,
54-
cpuinfo_arm_chipset_series_allwinner_a,
55-
cpuinfo_arm_chipset_series_amlogic_aml,
56-
cpuinfo_arm_chipset_series_amlogic_s,
57-
cpuinfo_arm_chipset_series_broadcom_bcm,
58-
cpuinfo_arm_chipset_series_lg_nuclun,
59-
cpuinfo_arm_chipset_series_leadcore_lc,
60-
cpuinfo_arm_chipset_series_marvell_pxa,
61-
cpuinfo_arm_chipset_series_mstar_6a,
62-
cpuinfo_arm_chipset_series_novathor_u,
63-
cpuinfo_arm_chipset_series_nvidia_tegra_t,
64-
cpuinfo_arm_chipset_series_nvidia_tegra_ap,
65-
cpuinfo_arm_chipset_series_nvidia_tegra_sl,
66-
cpuinfo_arm_chipset_series_pinecone_surge_s,
67-
cpuinfo_arm_chipset_series_renesas_mp,
68-
cpuinfo_arm_chipset_series_rockchip_rk,
69-
cpuinfo_arm_chipset_series_spreadtrum_sc,
70-
cpuinfo_arm_chipset_series_telechips_tcc,
71-
cpuinfo_arm_chipset_series_texas_instruments_omap,
72-
cpuinfo_arm_chipset_series_unisoc_t,
73-
cpuinfo_arm_chipset_series_unisoc_ums,
74-
cpuinfo_arm_chipset_series_wondermedia_wm,
75-
cpuinfo_arm_chipset_series_max,
43+
cpuinfo_arm_chipset_series_unknown = 0,
44+
cpuinfo_arm_chipset_series_qualcomm_qsd,
45+
cpuinfo_arm_chipset_series_qualcomm_msm,
46+
cpuinfo_arm_chipset_series_qualcomm_apq,
47+
cpuinfo_arm_chipset_series_qualcomm_snapdragon,
48+
cpuinfo_arm_chipset_series_mediatek_mt,
49+
cpuinfo_arm_chipset_series_samsung_exynos,
50+
cpuinfo_arm_chipset_series_hisilicon_k3v,
51+
cpuinfo_arm_chipset_series_hisilicon_hi,
52+
cpuinfo_arm_chipset_series_hisilicon_kirin,
53+
cpuinfo_arm_chipset_series_actions_atm,
54+
cpuinfo_arm_chipset_series_allwinner_a,
55+
cpuinfo_arm_chipset_series_amlogic_aml,
56+
cpuinfo_arm_chipset_series_amlogic_s,
57+
cpuinfo_arm_chipset_series_broadcom_bcm,
58+
cpuinfo_arm_chipset_series_lg_nuclun,
59+
cpuinfo_arm_chipset_series_leadcore_lc,
60+
cpuinfo_arm_chipset_series_marvell_pxa,
61+
cpuinfo_arm_chipset_series_mstar_6a,
62+
cpuinfo_arm_chipset_series_novathor_u,
63+
cpuinfo_arm_chipset_series_nvidia_tegra_t,
64+
cpuinfo_arm_chipset_series_nvidia_tegra_ap,
65+
cpuinfo_arm_chipset_series_nvidia_tegra_sl,
66+
cpuinfo_arm_chipset_series_pinecone_surge_s,
67+
cpuinfo_arm_chipset_series_renesas_mp,
68+
cpuinfo_arm_chipset_series_rockchip_rk,
69+
cpuinfo_arm_chipset_series_spreadtrum_sc,
70+
cpuinfo_arm_chipset_series_telechips_tcc,
71+
cpuinfo_arm_chipset_series_texas_instruments_omap,
72+
cpuinfo_arm_chipset_series_unisoc_t,
73+
cpuinfo_arm_chipset_series_unisoc_ums,
74+
cpuinfo_arm_chipset_series_wondermedia_wm,
75+
cpuinfo_arm_chipset_series_max,
7676
};
7777

7878
#define CPUINFO_ARM_CHIPSET_SUFFIX_MAX 8
7979

8080
struct cpuinfo_arm_chipset {
81-
enum cpuinfo_arm_chipset_vendor vendor;
82-
enum cpuinfo_arm_chipset_series series;
83-
uint32_t model;
84-
char suffix[CPUINFO_ARM_CHIPSET_SUFFIX_MAX];
81+
enum cpuinfo_arm_chipset_vendor vendor;
82+
enum cpuinfo_arm_chipset_series series;
83+
uint32_t model;
84+
char suffix[CPUINFO_ARM_CHIPSET_SUFFIX_MAX];
8585
};
8686

8787
#define CPUINFO_ARM_CHIPSET_NAME_MAX CPUINFO_PACKAGE_NAME_MAX
8888

8989
#ifndef __cplusplus
9090
CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string(
91-
const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
92-
char name[RESTRICT_STATIC CPUINFO_ARM_CHIPSET_NAME_MAX]);
91+
const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
92+
char name[RESTRICT_STATIC CPUINFO_ARM_CHIPSET_NAME_MAX]);
9393

94-
CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset(
95-
struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
96-
uint32_t cores,
97-
uint32_t max_cpu_freq_max);
94+
CPUINFO_INTERNAL void
95+
cpuinfo_arm_fixup_chipset(struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
96+
uint32_t cores, uint32_t max_cpu_freq_max);
9897

99-
CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch(
100-
uint32_t midr,
98+
CPUINFO_INTERNAL void
99+
cpuinfo_arm_decode_vendor_uarch(uint32_t midr,
101100
#if CPUINFO_ARCH_ARM
102-
bool has_vfpv4,
101+
bool has_vfpv4,
103102
#endif
104-
enum cpuinfo_vendor vendor[RESTRICT_STATIC 1],
105-
enum cpuinfo_uarch uarch[RESTRICT_STATIC 1]);
103+
enum cpuinfo_vendor vendor[RESTRICT_STATIC 1],
104+
enum cpuinfo_uarch uarch[RESTRICT_STATIC 1]);
106105

107106
CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
108-
enum cpuinfo_uarch uarch,
109-
uint32_t cluster_cores,
110-
uint32_t midr,
111-
const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
112-
uint32_t cluster_id,
113-
uint32_t arch_version,
114-
struct cpuinfo_cache l1i[RESTRICT_STATIC 1],
115-
struct cpuinfo_cache l1d[RESTRICT_STATIC 1],
116-
struct cpuinfo_cache l2[RESTRICT_STATIC 1],
117-
struct cpuinfo_cache l3[RESTRICT_STATIC 1]);
107+
enum cpuinfo_uarch uarch, uint32_t cluster_cores, uint32_t midr,
108+
const struct cpuinfo_arm_chipset chipset[RESTRICT_STATIC 1],
109+
uint32_t cluster_id, uint32_t arch_version,
110+
struct cpuinfo_cache l1i[RESTRICT_STATIC 1],
111+
struct cpuinfo_cache l1d[RESTRICT_STATIC 1],
112+
struct cpuinfo_cache l2[RESTRICT_STATIC 1],
113+
struct cpuinfo_cache l3[RESTRICT_STATIC 1]);
118114

119-
CPUINFO_INTERNAL uint32_t
120-
cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor processor[RESTRICT_STATIC 1]);
115+
CPUINFO_INTERNAL uint32_t cpuinfo_arm_compute_max_cache_size(
116+
const struct cpuinfo_processor processor[RESTRICT_STATIC 1]);
121117
#else /* defined(__cplusplus) */
122118
CPUINFO_INTERNAL void cpuinfo_arm_decode_cache(
123-
enum cpuinfo_uarch uarch,
124-
uint32_t cluster_cores,
125-
uint32_t midr,
126-
const struct cpuinfo_arm_chipset chipset[1],
127-
uint32_t cluster_id,
128-
uint32_t arch_version,
129-
struct cpuinfo_cache l1i[1],
130-
struct cpuinfo_cache l1d[1],
131-
struct cpuinfo_cache l2[1],
132-
struct cpuinfo_cache l3[1]);
119+
enum cpuinfo_uarch uarch, uint32_t cluster_cores, uint32_t midr,
120+
const struct cpuinfo_arm_chipset chipset[1], uint32_t cluster_id,
121+
uint32_t arch_version, struct cpuinfo_cache l1i[1],
122+
struct cpuinfo_cache l1d[1], struct cpuinfo_cache l2[1],
123+
struct cpuinfo_cache l3[1]);
133124
#endif

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