@@ -101,8 +101,6 @@ device. All fields are optional.
101101 u8 rx_threshold;
102102 u8 dma_burst_size;
103103 u32 timeout;
104- u8 enable_loopback;
105- void (*cs_control)(u32 command);
106104 };
107105
108106The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
@@ -128,16 +126,6 @@ dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
128126slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
129127timeouts and must busy-wait any trailing bytes.
130128
131- The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
132- into internal loopback mode. In this mode the SSP controller internally
133- connects the SSPTX pin to the SSPRX pin. This is useful for initial setup
134- testing.
135-
136- The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
137- function for asserting/deasserting a slave device chip select. If the field is
138- NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
139- configured to use GPIO or SSPFRM instead.
140-
141129NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
142130chipselect is dropped after each spi_transfer. Most devices need chip select
143131asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor)
@@ -152,38 +140,18 @@ field. Below is a sample configuration using the PXA255 NSSP.
152140
153141::
154142
155- /* Chip Select control for the CS8415A SPI slave device */
156- static void cs8415a_cs_control(u32 command)
157- {
158- if (command & PXA2XX_CS_ASSERT)
159- GPCR(2) = GPIO_bit(2);
160- else
161- GPSR(2) = GPIO_bit(2);
162- }
163-
164- /* Chip Select control for the CS8405A SPI slave device */
165- static void cs8405a_cs_control(u32 command)
166- {
167- if (command & PXA2XX_CS_ASSERT)
168- GPCR(3) = GPIO_bit(3);
169- else
170- GPSR(3) = GPIO_bit(3);
171- }
172-
173143 static struct pxa2xx_spi_chip cs8415a_chip_info = {
174144 .tx_threshold = 8, /* SSP hardward FIFO threshold */
175145 .rx_threshold = 8, /* SSP hardward FIFO threshold */
176146 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
177147 .timeout = 235, /* See Intel documentation */
178- .cs_control = cs8415a_cs_control, /* Use external chip select */
179148 };
180149
181150 static struct pxa2xx_spi_chip cs8405a_chip_info = {
182151 .tx_threshold = 8, /* SSP hardward FIFO threshold */
183152 .rx_threshold = 8, /* SSP hardward FIFO threshold */
184153 .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
185154 .timeout = 235, /* See Intel documentation */
186- .cs_control = cs8405a_cs_control, /* Use external chip select */
187155 };
188156
189157 static struct spi_board_info streetracer_spi_board_info[] __initdata = {
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