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Jocelyn Falempe
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drm/i915/pxp: add huc authentication and loading command
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2041690 Upstream Status: git://anongit.freedesktop.org/drm/drm commit 887a193 Author: Tomas Winkler <tomas.winkler@intel.com> AuthorDate: Tue Sep 27 17:41:39 2022 -0700 Commit: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> CommitDate: Mon Oct 3 11:29:15 2022 -0700 Add support for loading HuC via a pxp stream command. V4: 1. Remove unnecessary include in intel_pxp_huc.h (Jani) 2. Adjust copyright year to 2022 Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220928004145.745803-10-daniele.ceraolospurio@intel.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
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‎drivers/gpu/drm/i915/Makefile‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -310,7 +310,8 @@ i915-y += i915_perf.o
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# Protected execution platform (PXP) support. Base support is required for HuC
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i915-y += \
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pxp/intel_pxp.o \
313-
pxp/intel_pxp_tee.o
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pxp/intel_pxp_tee.o \
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pxp/intel_pxp_huc.o
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i915-$(CONFIG_DRM_I915_PXP) += \
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pxp/intel_pxp_cmd.o \

‎drivers/gpu/drm/i915/pxp/intel_pxp_huc.c‎

Lines changed: 69 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,69 @@
1+
// SPDX-License-Identifier: MIT
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/*
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* Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
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*/
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#include "drm/i915_drm.h"
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#include "i915_drv.h"
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#include "gem/i915_gem_region.h"
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#include "gt/intel_gt.h"
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#include "intel_pxp.h"
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#include "intel_pxp_huc.h"
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#include "intel_pxp_tee.h"
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#include "intel_pxp_types.h"
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#include "intel_pxp_tee_interface.h"
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int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp)
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{
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struct intel_gt *gt = pxp_to_gt(pxp);
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struct intel_huc *huc = &gt->uc.huc;
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struct pxp_tee_start_huc_auth_in huc_in = {0};
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struct pxp_tee_start_huc_auth_out huc_out = {0};
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dma_addr_t huc_phys_addr;
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u8 client_id = 0;
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u8 fence_id = 0;
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int err;
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if (!pxp->pxp_component)
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return -ENODEV;
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huc_phys_addr = i915_gem_object_get_dma_address(huc->fw.obj, 0);
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/* write the PXP message into the lmem (the sg list) */
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huc_in.header.api_version = PXP_TEE_43_APIVER;
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huc_in.header.command_id = PXP_TEE_43_START_HUC_AUTH;
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huc_in.header.status = 0;
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huc_in.header.buffer_len = sizeof(huc_in.huc_base_address);
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huc_in.huc_base_address = huc_phys_addr;
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err = intel_pxp_tee_stream_message(pxp, client_id, fence_id,
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&huc_in, sizeof(huc_in),
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&huc_out, sizeof(huc_out));
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if (err < 0) {
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drm_err(&gt->i915->drm,
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"Failed to send HuC load and auth command to GSC [%d]!\n",
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err);
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return err;
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}
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/*
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* HuC does sometimes survive suspend/resume (it depends on how "deep"
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* a sleep state the device reaches) so we can end up here on resume
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* with HuC already loaded, in which case the GSC will return
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* PXP_STATUS_OP_NOT_PERMITTED. We can therefore consider the GuC
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* correctly transferred in this scenario; if the same error is ever
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* returned with HuC not loaded we'll still catch it when we check the
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* authentication bit later.
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*/
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if (huc_out.header.status != PXP_STATUS_SUCCESS &&
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huc_out.header.status != PXP_STATUS_OP_NOT_PERMITTED) {
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drm_err(&gt->i915->drm,
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"HuC load failed with GSC error = 0x%x\n",
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huc_out.header.status);
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return -EPROTO;
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}
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return 0;
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}

‎drivers/gpu/drm/i915/pxp/intel_pxp_huc.h‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright(c) 2021-2022, Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_PXP_HUC_H__
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#define __INTEL_PXP_HUC_H__
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struct intel_pxp;
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int intel_pxp_huc_load_and_auth(struct intel_pxp *pxp);
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#endif /* __INTEL_PXP_HUC_H__ */

‎drivers/gpu/drm/i915/pxp/intel_pxp_tee_interface.h‎

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/* SPDX-License-Identifier: MIT */
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/*
3-
* Copyright(c) 2020, Intel Corporation. All rights reserved.
3+
* Copyright(c) 2020-2022, Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_PXP_TEE_INTERFACE_H__
@@ -9,8 +9,20 @@
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#include <linux/types.h>
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1111
#define PXP_TEE_APIVER 0x40002
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#define PXP_TEE_43_APIVER 0x00040003
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#define PXP_TEE_ARB_CMDID 0x1e
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#define PXP_TEE_ARB_PROTECTION_MODE 0x2
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#define PXP_TEE_43_START_HUC_AUTH 0x0000003A
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/*
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* there are a lot of status codes for PXP, but we only define the ones we
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* actually can handle in the driver. other failure codes will be printed to
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* error msg for debug.
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*/
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enum pxp_status {
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PXP_STATUS_SUCCESS = 0x0,
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PXP_STATUS_OP_NOT_PERMITTED = 0x4013
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};
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/* PXP TEE message header */
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struct pxp_tee_cmd_header {
@@ -33,4 +45,13 @@ struct pxp_tee_create_arb_out {
3345
struct pxp_tee_cmd_header header;
3446
} __packed;
3547

48+
struct pxp_tee_start_huc_auth_in {
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struct pxp_tee_cmd_header header;
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__le64 huc_base_address;
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};
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struct pxp_tee_start_huc_auth_out {
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struct pxp_tee_cmd_header header;
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};
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#endif /* __INTEL_PXP_TEE_INTERFACE_H__ */

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