clk: tegra: Fix Tegra PWM parent clock

Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2135064

commit c461c67
Author: Jon Hunter <jonathanh@nvidia.com>
Date: Mon, 10 Oct 2022 11:00:46 +0100

    Commit 8c193f4 ("pwm: tegra: Optimize period calculation") updated
    the period calculation in the Tegra PWM driver and now returns an error
    if the period requested is less than minimum period supported. This is
    breaking PWM support on various Tegra platforms. For example, on the
    Tegra210 Jetson Nano platform this is breaking the PWM fan support and
    probing the PWM fan driver now fails ...

     pwm-fan pwm-fan: Failed to configure PWM: -22
     pwm-fan: probe of pwm-fan failed with error -22

    The problem is that the default parent clock for the PWM on Tegra210 is
    a 32kHz clock and is unable to support the requested PWM period.

    Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
    updating the parent clock for the PWM to be the PLL_P.

    Fixes: 8c193f4 ("pwm: tegra: Optimize period calculation")
    Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
    Tested-by: Robert Eckelmann <longnoserob@gmail.com> # TF101 T20
    Tested-by: Antoni Aloy Torrens <aaloytorrens@gmail.com> # TF101 T20
    Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # TF201 T30
    Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # TF700T T3
    Link: https://lore.kernel.org/r/20221010100046.6477-1-jonathanh@nvidia.com
    Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>

Signed-off-by: Mark Salter <msalter@redhat.com>

Author: mosalter

drivers/clk/tegra/clk-tegra114.c

@@ -1166,6 +1166,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
 	{ TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
 	{ TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
+	{ TEGRA114_CLK_PWM, TEGRA114_CLK_PLL_P, 408000000, 0 },
 	/* must be the last entry */
 	{ TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
 };

drivers/clk/tegra/clk-tegra124.c

@@ -1330,6 +1330,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
 	{ TEGRA124_CLK_I2S3_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
 	{ TEGRA124_CLK_I2S4_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
 	{ TEGRA124_CLK_VIMCLK_SYNC, TEGRA124_CLK_CLK_MAX, 24576000, 0 },
+	{ TEGRA124_CLK_PWM, TEGRA124_CLK_PLL_P, 408000000, 0 },
 	/* must be the last entry */
 	{ TEGRA124_CLK_CLK_MAX, TEGRA124_CLK_CLK_MAX, 0, 0 },
 };

drivers/clk/tegra/clk-tegra20.c

@@ -1048,6 +1048,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
 	{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
 	{ TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 },
+	{ TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 },
 	/* must be the last entry */
 	{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
 };

drivers/clk/tegra/clk-tegra210.c

@@ -3597,6 +3597,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
 	{ TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
 	{ TEGRA210_CLK_HDA2CODEC_2X, TEGRA210_CLK_PLL_P, 48000000, 0 },
+	{ TEGRA210_CLK_PWM, TEGRA210_CLK_PLL_P, 48000000, 0 },
 	/* This MUST be the last entry. */
 	{ TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
 };

drivers/clk/tegra/clk-tegra30.c

@@ -1255,6 +1255,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
 	{ TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
 	{ TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 },
 	{ TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 },
+	{ TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 },
 	/* must be the last entry */
 	{ TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
 };