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Herton R. Krzesinski
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Merge: backport QDrive3 device tree and drivers/phy/qualcomm (6.2-rc2)
MR: https://gitlab.com/redhat/centos-stream/src/kernel/centos-stream-9/-/merge_requests/1855 Bugzilla: https://bugzilla.redhat.com/2159516 Depends: https://bugzilla.redhat.com/2158909 Backport QDrive3 device tree and drivers/phy/qualcomm (6.2-rc2). Those subsystems are intertwined and need to be updated together. Signed-off-by: Adrien Thierry <athierry@redhat.com> Approved-by: Andrew Halaney <ahalaney@redhat.com> Approved-by: Mark Langsdorf <mlangsdo@redhat.com> Approved-by: Eric Chanudet <echanude@redhat.com> Approved-by: Brian Masney <bmasney@redhat.com> Conflicts: drivers/clk/qcom/clk-rpmh.c Due already merged changes, solved conflicts by keeping them. Signed-off-by: Herton R. Krzesinski <herton@redhat.com>
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‎Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml‎

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm QMP USB4-USB3-DP PHY controller (SC8280XP)
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maintainers:
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- Vinod Koul <vkoul@kernel.org>
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description:
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The QMP PHY controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS and USB.
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properties:
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compatible:
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enum:
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- qcom,sc8280xp-qmp-usb43dp-phy
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reg:
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maxItems: 1
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clocks:
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maxItems: 4
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clock-names:
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items:
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- const: aux
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- const: ref
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- const: com_aux
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- const: usb3_pipe
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power-domains:
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maxItems: 1
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: phy
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- const: common
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vdda-phy-supply: true
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vdda-pll-supply: true
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"#clock-cells":
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const: 1
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description:
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See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
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"#phy-cells":
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const: 1
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description:
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See include/dt-bindings/dt-bindings/phy/phy-qcom-qmp.h
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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- resets
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- reset-names
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- vdda-phy-supply
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- vdda-pll-supply
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- "#clock-cells"
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
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phy@88eb000 {
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compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
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reg = <0x088eb000 0x4000>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB4_EUD_CLKREF_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "aux", "ref", "com_aux", "usb3_pipe";
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power-domains = <&gcc USB30_PRIM_GDSC>;
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resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
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<&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
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reset-names = "phy", "common";
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vdda-phy-supply = <&vreg_l9d>;
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vdda-pll-supply = <&vreg_l4d>;
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#clock-cells = <1>;
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#phy-cells = <1>;
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};

‎arch/arm64/boot/dts/qcom/Makefile‎

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dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
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dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb

‎arch/arm64/boot/dts/qcom/pm8450a.dtsi‎

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// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Linaro Limited
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*/
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#include <dt-bindings/spmi/spmi.h>
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&spmi_bus {
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pm8450a: pmic@0 {
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compatible = "qcom,pm8150", "qcom,spmi-pmic";
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reg = <0x0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8450a_gpios: gpio@c000 {
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compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
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reg = <0xc000>;
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gpio-controller;
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gpio-ranges = <&pm8450a_gpios 0 0 10>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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pm8450c: pmic@4 {
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compatible = "qcom,pm8150", "qcom,spmi-pmic";
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reg = <0x4 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8450c_gpios: gpio@c000 {
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compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
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reg = <0xc000>;
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gpio-controller;
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gpio-ranges = <&pm8450c_gpios 0 0 10>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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pm8450e: pmic@8 {
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compatible = "qcom,pm8150", "qcom,spmi-pmic";
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reg = <0x8 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8450e_gpios: gpio@c000 {
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compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
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reg = <0xc000>;
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gpio-controller;
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gpio-ranges = <&pm8450e_gpios 0 0 10>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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pm8450g: pmic@c {
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compatible = "qcom,pm8150", "qcom,spmi-pmic";
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reg = <0xc SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pm8450g_gpios: gpio@c000 {
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compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio";
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reg = <0xc000>;
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gpio-controller;
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gpio-ranges = <&pm8450g_gpios 0 0 10>;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};

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