Skip to content

Commit a095846

Browse files
author
Jocelyn Falempe
committed
drm/i915/huc: stall media submission until HuC is loaded
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2041690 Upstream Status: git://anongit.freedesktop.org/drm/drm commit e6177ec Author: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> AuthorDate: Tue Sep 27 17:41:42 2022 -0700 Commit: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> CommitDate: Mon Oct 3 11:29:19 2022 -0700 Wait on the fence to be signalled to avoid the submissions finding HuC not yet loaded. v2: use dedicaded wait_queue_entry for waiting in HuC load, as submitq can't be re-used for it. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Tony Ye <tony.ye@intel.com> Acked-by: Tony Ye <tony.ye@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220928004145.745803-13-daniele.ceraolospurio@intel.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
1 parent 9694bd7 commit a095846

File tree

3 files changed

+35
-0
lines changed

3 files changed

+35
-0
lines changed

drivers/gpu/drm/i915/gt/uc/intel_huc.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc)
8181
return huc->fw.loaded_via_gsc;
8282
}
8383

84+
static inline bool intel_huc_wait_required(struct intel_huc *huc)
85+
{
86+
return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) &&
87+
!intel_huc_is_authenticated(huc);
88+
}
89+
8490
void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
8591

8692
#endif

drivers/gpu/drm/i915/i915_request.c

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to,
16211621
return ret;
16221622
}
16231623

1624+
static void i915_request_await_huc(struct i915_request *rq)
1625+
{
1626+
struct intel_huc *huc = &rq->context->engine->gt->uc.huc;
1627+
1628+
/* don't stall kernel submissions! */
1629+
if (!rcu_access_pointer(rq->context->gem_context))
1630+
return;
1631+
1632+
if (intel_huc_wait_required(huc))
1633+
i915_sw_fence_await_sw_fence(&rq->submit,
1634+
&huc->delayed_load.fence,
1635+
&rq->hucq);
1636+
}
1637+
16241638
static struct i915_request *
16251639
__i915_request_ensure_parallel_ordering(struct i915_request *rq,
16261640
struct intel_timeline *timeline)
@@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq)
17021716
struct intel_timeline *timeline = i915_request_timeline(rq);
17031717
struct i915_request *prev;
17041718

1719+
/*
1720+
* Media workloads may require HuC, so stall them until HuC loading is
1721+
* complete. Note that HuC not being loaded when a user submission
1722+
* arrives can only happen when HuC is loaded via GSC and in that case
1723+
* we still expect the window between us starting to accept submissions
1724+
* and HuC loading completion to be small (a few hundred ms).
1725+
*/
1726+
if (rq->engine->class == VIDEO_DECODE_CLASS)
1727+
i915_request_await_huc(rq);
1728+
17051729
/*
17061730
* Dependency tracking and request ordering along the timeline
17071731
* is special cased so that we can eliminate redundant ordering

drivers/gpu/drm/i915/i915_request.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,11 @@ struct i915_request {
348348
#define GUC_PRIO_FINI 0xfe
349349
u8 guc_prio;
350350

351+
/**
352+
* @hucq: wait queue entry used to wait on the HuC load to complete
353+
*/
354+
wait_queue_entry_t hucq;
355+
351356
I915_SELFTEST_DECLARE(struct {
352357
struct list_head link;
353358
unsigned long delay;

0 commit comments

Comments
 (0)