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x86/bugs: Add "unknown" reporting for MMIO Stale Data
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2138389 Conflicts: A fuzz inarch/x86/kernel/cpu/common.c due to missing upstream commit 639475d ("x86/CPU: Add support for Vortex CPUs"). commit 7df5488 Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Date: Wed, 3 Aug 2022 14:41:32 -0700 x86/bugs: Add "unknown" reporting for MMIO Stale Data Older Intel CPUs that are not in the affected processor list for MMIO Stale Data vulnerabilities currently report "Not affected" in sysfs, which may not be correct. Vulnerability status for these older CPUs is unknown. Add known-not-affected CPUs to the whitelist. Report "unknown" mitigation status for CPUs that are not in blacklist, whitelist and also don't enumerate MSR ARCH_CAPABILITIES bits that reflect hardware immunity to MMIO Stale Data vulnerabilities. Mitigation is not deployed when the status is unknown. [ bp: Massage, fixup. ] Fixes: 8d50cdf ("x86/speculation/mmio: Add sysfs reporting for Processor MMIO Stale Data") Suggested-by: Andrew Cooper <andrew.cooper3@citrix.com> Suggested-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/a932c154772f2121794a5f2eded1a11013114711.1657846269.git.pawan.kumar.gupta@linux.intel.com Signed-off-by: Waiman Long <longman@redhat.com>
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‎Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -230,6 +230,20 @@ The possible values in this file are:
230230
* - 'Mitigation: Clear CPU buffers'
231231
- The processor is vulnerable and the CPU buffer clearing mitigation is
232232
enabled.
233+
* - 'Unknown: No mitigations'
234+
- The processor vulnerability status is unknown because it is
235+
out of Servicing period. Mitigation is not attempted.
236+
237+
Definitions:
238+
------------
239+
240+
Servicing period: The process of providing functional and security updates to
241+
Intel processors or platforms, utilizing the Intel Platform Update (IPU)
242+
process or other similar mechanisms.
243+
244+
End of Servicing Updates (ESU): ESU is the date at which Intel will no
245+
longer provide Servicing, such as through IPU or other similar update
246+
processes. ESU dates will typically be aligned to end of quarter.
233247

234248
If the processor is vulnerable then the following information is appended to
235249
the above information:

‎arch/x86/include/asm/cpufeatures.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -456,7 +456,8 @@
456456
#define X86_BUG_ITLB_MULTIHIT X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
457457
#define X86_BUG_SRBDS X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
458458
#define X86_BUG_MMIO_STALE_DATA X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
459-
#define X86_BUG_RETBLEED X86_BUG(26) /* CPU is affected by RETBleed */
460-
#define X86_BUG_EIBRS_PBRSB X86_BUG(27) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
459+
#define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
460+
#define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */
461+
#define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
461462

462463
#endif /* _ASM_X86_CPUFEATURES_H */

‎arch/x86/kernel/cpu/bugs.c‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -433,7 +433,8 @@ static void __init mmio_select_mitigation(void)
433433
u64 ia32_cap;
434434

435435
if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
436-
cpu_mitigations_off()) {
436+
boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
437+
cpu_mitigations_off()) {
437438
mmio_mitigation = MMIO_MITIGATION_OFF;
438439
return;
439440
}
@@ -538,6 +539,8 @@ static void __init md_clear_update_mitigation(void)
538539
pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
539540
if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
540541
pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
542+
else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
543+
pr_info("MMIO Stale Data: Unknown: No mitigations\n");
541544
}
542545

543546
static void __init md_clear_select_mitigation(void)
@@ -2267,6 +2270,9 @@ static ssize_t tsx_async_abort_show_state(char *buf)
22672270

22682271
static ssize_t mmio_stale_data_show_state(char *buf)
22692272
{
2273+
if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2274+
return sysfs_emit(buf, "Unknown: No mitigations\n");
2275+
22702276
if (mmio_mitigation == MMIO_MITIGATION_OFF)
22712277
return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
22722278

@@ -2412,6 +2418,7 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr
24122418
return srbds_show_state(buf);
24132419

24142420
case X86_BUG_MMIO_STALE_DATA:
2421+
case X86_BUG_MMIO_UNKNOWN:
24152422
return mmio_stale_data_show_state(buf);
24162423

24172424
case X86_BUG_RETBLEED:
@@ -2471,7 +2478,10 @@ ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *
24712478

24722479
ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
24732480
{
2474-
return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2481+
if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2482+
return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2483+
else
2484+
return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
24752485
}
24762486

24772487
ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)

‎arch/x86/kernel/cpu/common.c‎

Lines changed: 27 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1106,7 +1106,8 @@ static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
11061106
#define NO_SWAPGS BIT(6)
11071107
#define NO_ITLB_MULTIHIT BIT(7)
11081108
#define NO_SPECTRE_V2 BIT(8)
1109-
#define NO_EIBRS_PBRSB BIT(9)
1109+
#define NO_MMIO BIT(9)
1110+
#define NO_EIBRS_PBRSB BIT(10)
11101111

11111112
#define VULNWL(vendor, family, model, whitelist) \
11121113
X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
@@ -1127,6 +1128,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
11271128
VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
11281129

11291130
/* Intel Family 6 */
1131+
VULNWL_INTEL(TIGERLAKE, NO_MMIO),
1132+
VULNWL_INTEL(TIGERLAKE_L, NO_MMIO),
1133+
VULNWL_INTEL(ALDERLAKE, NO_MMIO),
1134+
VULNWL_INTEL(ALDERLAKE_L, NO_MMIO),
1135+
11301136
VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
11311137
VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
11321138
VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
@@ -1145,9 +1151,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
11451151
VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
11461152
VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
11471153

1148-
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1149-
VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1150-
VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1154+
VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1155+
VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1156+
VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
11511157

11521158
/*
11531159
* Technically, swapgs isn't serializing on AMD (despite it previously
@@ -1162,18 +1168,18 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
11621168
VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
11631169

11641170
/* AMD Family 0xf - 0x12 */
1165-
VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1166-
VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1167-
VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1168-
VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1171+
VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1172+
VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1173+
VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1174+
VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
11691175

11701176
/* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1171-
VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1172-
VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT),
1177+
VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1178+
VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
11731179

11741180
/* Zhaoxin Family 7 */
1175-
VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1176-
VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS),
1181+
VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
1182+
VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO),
11771183
{}
11781184
};
11791185

@@ -1327,10 +1333,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
13271333
* Affected CPU list is generally enough to enumerate the vulnerability,
13281334
* but for virtualization case check for ARCH_CAP MSR bits also, VMM may
13291335
* not want the guest to enumerate the bug.
1336+
*
1337+
* Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1338+
* nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
13301339
*/
1331-
if (cpu_matches(cpu_vuln_blacklist, MMIO) &&
1332-
!arch_cap_mmio_immune(ia32_cap))
1333-
setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1340+
if (!arch_cap_mmio_immune(ia32_cap)) {
1341+
if (cpu_matches(cpu_vuln_blacklist, MMIO))
1342+
setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1343+
else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1344+
setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1345+
}
13341346

13351347
if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
13361348
if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (ia32_cap & ARCH_CAP_RSBA))

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