Skip to content

Commit 558aafc

Browse files
athierry1athierry1
committed
clk: qcom: mmcc-msm8974: move clock parent tables down
Bugzilla: https://bugzilla.redhat.com/2158909 commit 28c6c02 Author: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Date: Sun Dec 4 14:45:04 2022 +0200 clk: qcom: mmcc-msm8974: move clock parent tables down Move clock parent tables down, after the PLL declarataions, so that we can use pll hw clock fields in the next commit. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221204124508.1415713-8-dmitry.baryshkov@linaro.org Signed-off-by: Adrien Thierry <athierry@redhat.com>
1 parent bc45771 commit 558aafc

File tree

1 file changed

+85
-85
lines changed

1 file changed

+85
-85
lines changed

‎drivers/clk/qcom/mmcc-msm8974.c‎

Lines changed: 85 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,91 @@ enum {
4242
P_DSI1PLL_BYTE,
4343
};
4444

45+
static struct clk_pll mmpll0 = {
46+
.l_reg = 0x0004,
47+
.m_reg = 0x0008,
48+
.n_reg = 0x000c,
49+
.config_reg = 0x0014,
50+
.mode_reg = 0x0000,
51+
.status_reg = 0x001c,
52+
.status_bit = 17,
53+
.clkr.hw.init = &(struct clk_init_data){
54+
.name = "mmpll0",
55+
.parent_names = (const char *[]){ "xo" },
56+
.num_parents = 1,
57+
.ops = &clk_pll_ops,
58+
},
59+
};
60+
61+
static struct clk_regmap mmpll0_vote = {
62+
.enable_reg = 0x0100,
63+
.enable_mask = BIT(0),
64+
.hw.init = &(struct clk_init_data){
65+
.name = "mmpll0_vote",
66+
.parent_names = (const char *[]){ "mmpll0" },
67+
.num_parents = 1,
68+
.ops = &clk_pll_vote_ops,
69+
},
70+
};
71+
72+
static struct clk_pll mmpll1 = {
73+
.l_reg = 0x0044,
74+
.m_reg = 0x0048,
75+
.n_reg = 0x004c,
76+
.config_reg = 0x0050,
77+
.mode_reg = 0x0040,
78+
.status_reg = 0x005c,
79+
.status_bit = 17,
80+
.clkr.hw.init = &(struct clk_init_data){
81+
.name = "mmpll1",
82+
.parent_names = (const char *[]){ "xo" },
83+
.num_parents = 1,
84+
.ops = &clk_pll_ops,
85+
},
86+
};
87+
88+
static struct clk_regmap mmpll1_vote = {
89+
.enable_reg = 0x0100,
90+
.enable_mask = BIT(1),
91+
.hw.init = &(struct clk_init_data){
92+
.name = "mmpll1_vote",
93+
.parent_names = (const char *[]){ "mmpll1" },
94+
.num_parents = 1,
95+
.ops = &clk_pll_vote_ops,
96+
},
97+
};
98+
99+
static struct clk_pll mmpll2 = {
100+
.l_reg = 0x4104,
101+
.m_reg = 0x4108,
102+
.n_reg = 0x410c,
103+
.config_reg = 0x4110,
104+
.mode_reg = 0x4100,
105+
.status_reg = 0x411c,
106+
.clkr.hw.init = &(struct clk_init_data){
107+
.name = "mmpll2",
108+
.parent_names = (const char *[]){ "xo" },
109+
.num_parents = 1,
110+
.ops = &clk_pll_ops,
111+
},
112+
};
113+
114+
static struct clk_pll mmpll3 = {
115+
.l_reg = 0x0084,
116+
.m_reg = 0x0088,
117+
.n_reg = 0x008c,
118+
.config_reg = 0x0090,
119+
.mode_reg = 0x0080,
120+
.status_reg = 0x009c,
121+
.status_bit = 17,
122+
.clkr.hw.init = &(struct clk_init_data){
123+
.name = "mmpll3",
124+
.parent_names = (const char *[]){ "xo" },
125+
.num_parents = 1,
126+
.ops = &clk_pll_ops,
127+
},
128+
};
129+
45130
static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
46131
{ P_XO, 0 },
47132
{ P_MMPLL0, 1 },
@@ -160,91 +245,6 @@ static const char * const mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
160245
"dsi1pllbyte",
161246
};
162247

163-
static struct clk_pll mmpll0 = {
164-
.l_reg = 0x0004,
165-
.m_reg = 0x0008,
166-
.n_reg = 0x000c,
167-
.config_reg = 0x0014,
168-
.mode_reg = 0x0000,
169-
.status_reg = 0x001c,
170-
.status_bit = 17,
171-
.clkr.hw.init = &(struct clk_init_data){
172-
.name = "mmpll0",
173-
.parent_names = (const char *[]){ "xo" },
174-
.num_parents = 1,
175-
.ops = &clk_pll_ops,
176-
},
177-
};
178-
179-
static struct clk_regmap mmpll0_vote = {
180-
.enable_reg = 0x0100,
181-
.enable_mask = BIT(0),
182-
.hw.init = &(struct clk_init_data){
183-
.name = "mmpll0_vote",
184-
.parent_names = (const char *[]){ "mmpll0" },
185-
.num_parents = 1,
186-
.ops = &clk_pll_vote_ops,
187-
},
188-
};
189-
190-
static struct clk_pll mmpll1 = {
191-
.l_reg = 0x0044,
192-
.m_reg = 0x0048,
193-
.n_reg = 0x004c,
194-
.config_reg = 0x0050,
195-
.mode_reg = 0x0040,
196-
.status_reg = 0x005c,
197-
.status_bit = 17,
198-
.clkr.hw.init = &(struct clk_init_data){
199-
.name = "mmpll1",
200-
.parent_names = (const char *[]){ "xo" },
201-
.num_parents = 1,
202-
.ops = &clk_pll_ops,
203-
},
204-
};
205-
206-
static struct clk_regmap mmpll1_vote = {
207-
.enable_reg = 0x0100,
208-
.enable_mask = BIT(1),
209-
.hw.init = &(struct clk_init_data){
210-
.name = "mmpll1_vote",
211-
.parent_names = (const char *[]){ "mmpll1" },
212-
.num_parents = 1,
213-
.ops = &clk_pll_vote_ops,
214-
},
215-
};
216-
217-
static struct clk_pll mmpll2 = {
218-
.l_reg = 0x4104,
219-
.m_reg = 0x4108,
220-
.n_reg = 0x410c,
221-
.config_reg = 0x4110,
222-
.mode_reg = 0x4100,
223-
.status_reg = 0x411c,
224-
.clkr.hw.init = &(struct clk_init_data){
225-
.name = "mmpll2",
226-
.parent_names = (const char *[]){ "xo" },
227-
.num_parents = 1,
228-
.ops = &clk_pll_ops,
229-
},
230-
};
231-
232-
static struct clk_pll mmpll3 = {
233-
.l_reg = 0x0084,
234-
.m_reg = 0x0088,
235-
.n_reg = 0x008c,
236-
.config_reg = 0x0090,
237-
.mode_reg = 0x0080,
238-
.status_reg = 0x009c,
239-
.status_bit = 17,
240-
.clkr.hw.init = &(struct clk_init_data){
241-
.name = "mmpll3",
242-
.parent_names = (const char *[]){ "xo" },
243-
.num_parents = 1,
244-
.ops = &clk_pll_ops,
245-
},
246-
};
247-
248248
static struct clk_rcg2 mmss_ahb_clk_src = {
249249
.cmd_rcgr = 0x5000,
250250
.hid_width = 5,

0 commit comments

Comments
 (0)