|
31 | 31 |
|
32 | 32 | #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) |
33 | 33 |
|
34 | | -#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE |
35 | | -#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled |
| 34 | +#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUD_DWC2_DMA_ENABLE) |
| 35 | +#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUD_DWC2_DMA_ENABLE to be enabled |
36 | 36 | #endif |
37 | 37 |
|
38 | 38 | // Debug level for DWC2 |
@@ -192,8 +192,8 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { |
192 | 192 | } |
193 | 193 | } else { |
194 | 194 | // Check IN endpoints concurrently active limit |
195 | | - if(_dwc2_controller->ep_in_count) { |
196 | | - TU_ASSERT(_dcd_data.allocated_epin_count < _dwc2_controller->ep_in_count); |
| 195 | + if(dwc2_controller->ep_in_count) { |
| 196 | + TU_ASSERT(_dcd_data.allocated_epin_count < dwc2_controller->ep_in_count); |
197 | 197 | _dcd_data.allocated_epin_count++; |
198 | 198 | } |
199 | 199 |
|
@@ -561,7 +561,7 @@ void dcd_edpt_close_all(uint8_t rhport) { |
561 | 561 | dwc2_regs_t* dwc2 = DWC2_REG(rhport); |
562 | 562 | uint8_t const ep_count = _dwc2_controller[rhport].ep_count; |
563 | 563 |
|
564 | | - _dcd_data.allocated_epin_count = 1; |
| 564 | + _dcd_data.allocated_epin_count = 0; |
565 | 565 |
|
566 | 566 | // Disable non-control interrupt |
567 | 567 | dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); |
@@ -641,10 +641,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t |
641 | 641 | return true; |
642 | 642 | } |
643 | 643 |
|
644 | | -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { |
645 | | - edpt_disable(rhport, ep_addr, false); |
646 | | -} |
647 | | - |
648 | 644 | void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { |
649 | 645 | dwc2_regs_t* dwc2 = DWC2_REG(rhport); |
650 | 646 | edpt_disable(rhport, ep_addr, true); |
@@ -676,7 +672,7 @@ static void handle_bus_reset(uint8_t rhport) { |
676 | 672 | tu_memclr(xfer_status, sizeof(xfer_status)); |
677 | 673 |
|
678 | 674 | _dcd_data.sof_en = false; |
679 | | - _dcd_data.allocated_epin_count = 1; |
| 675 | + _dcd_data.allocated_epin_count = 0; |
680 | 676 |
|
681 | 677 | // 1. NAK for all OUT endpoints |
682 | 678 | for (uint8_t n = 0; n < ep_count; n++) { |
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