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[WB] Update STM32WBxx CMSIS to v1.3.0
Included in STM32CubeWB FW V1.3.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 81418e2 commit d516634

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9 files changed

+141
-69
lines changed

9 files changed

+141
-69
lines changed

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb50xx.h‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -270,7 +270,7 @@ typedef struct
270270
typedef struct
271271
{
272272
__IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */
273-
__IO uint32_t PDKEYR; /*!< FLASH Power-down in run mode flash key Address offset: 0x04 */
273+
__IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */
274274
__IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
275275
__IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
276276
__IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
@@ -774,7 +774,8 @@ typedef struct
774774
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
775775
#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */
776776

777-
/* Size SRAMx */
777+
/* Memory Size */
778+
#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
778779
#define SRAM1_SIZE 0x00010000UL /*!< SRAM1 default size : 64 kB */
779780
#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */
780781
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
@@ -3838,7 +3839,7 @@ typedef struct
38383839
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */
38393840
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
38403841
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
3841-
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option bute loading */
3842+
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
38423843
#define FLASH_CR_OPTLOCK_Pos (30U)
38433844
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
38443845
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */
@@ -6430,7 +6431,8 @@ typedef struct
64306431
/*
64316432
* @brief Specific device feature definitions
64326433
*/
6433-
#define RCC_PLLSAI_SUPPORT
6434+
#define RCC_MCO3_SUPPORT
6435+
#define RCC_LSCO3_SUPPORT
64346436

64356437
/******************** Bit definition for RCC_CR register *****************/
64366438
#define RCC_CR_MSION_Pos (0U)
@@ -11164,9 +11166,6 @@ typedef struct
1116411166
((INSTANCE) == TIM16) || \
1116511167
((INSTANCE) == TIM17))
1116611168

11167-
/****************** TIM Instances : supporting synchronization ****************/
11168-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
11169-
1117011169
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1117111170
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1117211171

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wb55xx.h‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,7 @@ typedef struct
302302
typedef struct
303303
{
304304
__IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */
305-
__IO uint32_t PDKEYR; /*!< FLASH Power-down in run mode flash key Address offset: 0x04 */
305+
__IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */
306306
__IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
307307
__IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
308308
__IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
@@ -932,7 +932,8 @@ typedef struct
932932
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
933933
#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */
934934

935-
/* Size SRAMx */
935+
/* Memory Size */
936+
#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
936937
#define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */
937938
#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */
938939
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
@@ -4127,7 +4128,7 @@ typedef struct
41274128
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */
41284129
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
41294130
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
4130-
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option bute loading */
4131+
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
41314132
#define FLASH_CR_OPTLOCK_Pos (30U)
41324133
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
41334134
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */
@@ -7266,7 +7267,8 @@ typedef struct
72667267
* @brief Specific device feature definitions
72677268
*/
72687269
#define RCC_SMPS_SUPPORT
7269-
#define RCC_PLLSAI_SUPPORT
7270+
#define RCC_MCO3_SUPPORT
7271+
#define RCC_LSCO3_SUPPORT
72707272

72717273
/******************** Bit definition for RCC_CR register *****************/
72727274
#define RCC_CR_MSION_Pos (0U)
@@ -13634,9 +13636,6 @@ typedef struct
1363413636
((INSTANCE) == TIM16) || \
1363513637
((INSTANCE) == TIM17))
1363613638

13637-
/****************** TIM Instances : supporting synchronization ****************/
13638-
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
13639-
1364013639
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
1364113640
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
1364213641

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Include/stm32wbxx.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@
6969
* @brief CMSIS Device version number
7070
*/
7171
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
72-
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
72+
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
7373
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
7474
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
7575
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Release_Notes.html‎

Lines changed: 43 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -49,20 +49,58 @@ <h1 id="purpose">Purpose</h1>
4949
<div class="col-sm-12 col-lg-8">
5050
<h1 id="update-history">Update History</h1>
5151
<div class="collapse">
52-
<input type="checkbox" id="collapse-section3" checked aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
52+
<input type="checkbox" id="collapse-section4" checked aria-hidden="true"> <label for="collapse-section4" aria-hidden="true">v1.3.0 / 11-September-2019</label>
5353
<div>
5454
<h2 id="main-changes">Main Changes</h2>
55+
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx and stm32wb50xx devices)</p>
56+
<table>
57+
<thead>
58+
<tr class="header">
59+
<th style="text-align: left;">Fixed bugs headline</th>
60+
</tr>
61+
</thead>
62+
<tbody>
63+
<tr class="odd">
64+
<td style="text-align: left;">Remove IS_TIM_SYNCHRO_INSTANCE macro from CMSIS</td>
65+
</tr>
66+
<tr class="even">
67+
<td style="text-align: left;">Move FLASH_SIZE define from hal flash. h to cmsis device file</td>
68+
</tr>
69+
<tr class="odd">
70+
<td style="text-align: left;">Correct size of .bin files generated by SW4STM32</td>
71+
</tr>
72+
<tr class="even">
73+
<td style="text-align: left;">Remove RCC_PLLSAI_SUPPORT for STM32WB50</td>
74+
</tr>
75+
</tbody>
76+
</table>
77+
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
78+
<ul>
79+
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
80+
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
81+
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
82+
</ul>
83+
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
84+
<ul>
85+
<li>STM32WB55xx, STM32WB50xx devices</li>
86+
</ul>
87+
</div>
88+
</div>
89+
<div class="collapse">
90+
<input type="checkbox" id="collapse-section3" aria-hidden="true"> <label for="collapse-section3" aria-hidden="true">V1.2.0 / 26-June-2019</label>
91+
<div>
92+
<h2 id="main-changes-1">Main Changes</h2>
5593
<h3 id="introduction-of-stm32wb50xx-device">Introduction of STM32WB50xx device</h3>
5694
<p>First release for STM32WBxx CMSIS introducing <strong>stm32wb50xx</strong> devices.</p>
5795
<h2 id="contents">Contents</h2>
5896
<p>CMSIS devices files for stm32wb55xx, stm32wb50xx devices.</p>
59-
<h2 id="development-toolchains-and-compilers">Development Toolchains and Compilers</h2>
97+
<h2 id="development-toolchains-and-compilers-1">Development Toolchains and Compilers</h2>
6098
<ul>
6199
<li>IAR Embedded Workbench for ARM (EWARM) toolchain V8.20.2</li>
62100
<li>RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.25</li>
63101
<li>System Workbench STM32 (SW4STM32) toolchain V2.7</li>
64102
</ul>
65-
<h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
103+
<h2 id="supported-devices-and-boards-1">Supported Devices and boards</h2>
66104
<ul>
67105
<li>STM32WB55xx and STM32WB50xx devices</li>
68106
</ul>
@@ -71,7 +109,7 @@ <h2 id="supported-devices-and-boards">Supported Devices and boards</h2>
71109
<div class="collapse">
72110
<input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true">V1.1.0 / 05-April-2019</label>
73111
<div>
74-
<h2 id="main-changes-1">Main Changes</h2>
112+
<h2 id="main-changes-2">Main Changes</h2>
75113
<h3 id="maintenance-release">Maintenance release</h3>
76114
<p>Maintenance release for <strong>STM32WBxx</strong> devices (stm32wb55xx devices)</p>
77115
<table>
@@ -95,7 +133,7 @@ <h3 id="maintenance-release">Maintenance release</h3>
95133
<div class="collapse">
96134
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true">V1.0.0 / 06-February-2019</label>
97135
<div>
98-
<h2 id="main-changes-2">Main Changes</h2>
136+
<h2 id="main-changes-3">Main Changes</h2>
99137
<h3 id="first-release">First release</h3>
100138
<p>Add support of STM32WB55xx.</p>
101139
</div>

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb50xx_flash_cm4.ld‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,7 @@ SECTIONS
181181
.ARM.attributes 0 : { *(.ARM.attributes) }
182182
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
183183
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
184-
MB_MEM2 : { *(MB_MEM2) } >RAM_SHARED
184+
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
185185
}
186186

187187

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,7 @@ SECTIONS
181181
.ARM.attributes 0 : { *(.ARM.attributes) }
182182
MAPPING_TABLE (NOLOAD) : { *(MAPPING_TABLE) } >RAM_SHARED
183183
MB_MEM1 (NOLOAD) : { *(MB_MEM1) } >RAM_SHARED
184-
MB_MEM2 : { *(MB_MEM2) } >RAM_SHARED
184+
MB_MEM2 (NOLOAD) : { _sMB_MEM2 = . ; *(MB_MEM2) ; _eMB_MEM2 = . ; } >RAM_SHARED
185185
}
186186

187187

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb50xx_cm4.s‎

Lines changed: 41 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -44,21 +44,29 @@ defined in linker script */
4444
.word _sbss
4545
/* end address for the .bss section. defined in linker script */
4646
.word _ebss
47-
48-
.section .text.Reset_Handler
49-
.weak Reset_Handler
50-
.type Reset_Handler, %function
51-
Reset_Handler:
52-
ldr r0, =_estack
53-
mov sp, r0 /* set stack pointer */
54-
55-
/* Copy the data segment initializers from flash to SRAM */
56-
ldr r0, =_sdata
57-
ldr r1, =_edata
58-
ldr r2, =_sidata
47+
/* start address for the .MB_MEM2 section. defined in linker script */
48+
.word _sMB_MEM2
49+
/* end address for the .MB_MEM2 section. defined in linker script */
50+
.word _eMB_MEM2
51+
52+
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
53+
.macro INIT_BSS start, end
54+
ldr r0, =\start
55+
ldr r1, =\end
5956
movs r3, #0
60-
b LoopCopyDataInit
57+
bl LoopFillZerobss
58+
.endm
59+
60+
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
61+
.macro INIT_DATA start, end, src
62+
ldr r0, =\start
63+
ldr r1, =\end
64+
ldr r2, =\src
65+
movs r3, #0
66+
bl LoopCopyDataInit
67+
.endm
6168

69+
.section .text.data_initializers
6270
CopyDataInit:
6371
ldr r4, [r2, r3]
6472
str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
6775
LoopCopyDataInit:
6876
adds r4, r0, r3
6977
cmp r4, r1
70-
bcc CopyDataInit
71-
72-
/* Zero fill the bss segment. */
73-
ldr r2, =_sbss
74-
ldr r4, =_ebss
75-
movs r3, #0
76-
b LoopFillZerobss
78+
bcc CopyDataInit
79+
bx lr
7780

7881
FillZerobss:
79-
str r3, [r2]
80-
adds r2, r2, #4
82+
str r3, [r0]
83+
adds r0, r0, #4
8184

8285
LoopFillZerobss:
83-
cmp r2, r4
86+
cmp r0, r1
8487
bcc FillZerobss
88+
bx lr
89+
90+
.section .text.Reset_Handler
91+
.weak Reset_Handler
92+
.type Reset_Handler, %function
93+
Reset_Handler:
94+
ldr r0, =_estack
95+
mov sp, r0 /* set stack pointer */
96+
97+
/* Copy the data segment initializers from flash to SRAM */
98+
INIT_DATA _sdata, _edata, _sidata
99+
100+
/* Zero fill the bss segments. */
101+
INIT_BSS _sbss, _ebss
102+
INIT_BSS _sMB_MEM2, _eMB_MEM2
85103

86104
/* Call the clock system intitialization function.*/
87105
bl SystemInit

‎system/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/startup_stm32wb55xx_cm4.s‎

Lines changed: 41 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -44,21 +44,29 @@ defined in linker script */
4444
.word _sbss
4545
/* end address for the .bss section. defined in linker script */
4646
.word _ebss
47-
48-
.section .text.Reset_Handler
49-
.weak Reset_Handler
50-
.type Reset_Handler, %function
51-
Reset_Handler:
52-
ldr r0, =_estack
53-
mov sp, r0 /* set stack pointer */
54-
55-
/* Copy the data segment initializers from flash to SRAM */
56-
ldr r0, =_sdata
57-
ldr r1, =_edata
58-
ldr r2, =_sidata
47+
/* start address for the .MB_MEM2 section. defined in linker script */
48+
.word _sMB_MEM2
49+
/* end address for the .MB_MEM2 section. defined in linker script */
50+
.word _eMB_MEM2
51+
52+
/* INIT_BSS macro is used to fill the specified region [start : end] with zeros */
53+
.macro INIT_BSS start, end
54+
ldr r0, =\start
55+
ldr r1, =\end
5956
movs r3, #0
60-
b LoopCopyDataInit
57+
bl LoopFillZerobss
58+
.endm
59+
60+
/* INIT_DATA macro is used to copy data in the region [start : end] starting from 'src' */
61+
.macro INIT_DATA start, end, src
62+
ldr r0, =\start
63+
ldr r1, =\end
64+
ldr r2, =\src
65+
movs r3, #0
66+
bl LoopCopyDataInit
67+
.endm
6168

69+
.section .text.data_initializers
6270
CopyDataInit:
6371
ldr r4, [r2, r3]
6472
str r4, [r0, r3]
@@ -67,21 +75,31 @@ CopyDataInit:
6775
LoopCopyDataInit:
6876
adds r4, r0, r3
6977
cmp r4, r1
70-
bcc CopyDataInit
71-
72-
/* Zero fill the bss segment. */
73-
ldr r2, =_sbss
74-
ldr r4, =_ebss
75-
movs r3, #0
76-
b LoopFillZerobss
78+
bcc CopyDataInit
79+
bx lr
7780

7881
FillZerobss:
79-
str r3, [r2]
80-
adds r2, r2, #4
82+
str r3, [r0]
83+
adds r0, r0, #4
8184

8285
LoopFillZerobss:
83-
cmp r2, r4
86+
cmp r0, r1
8487
bcc FillZerobss
88+
bx lr
89+
90+
.section .text.Reset_Handler
91+
.weak Reset_Handler
92+
.type Reset_Handler, %function
93+
Reset_Handler:
94+
ldr r0, =_estack
95+
mov sp, r0 /* set stack pointer */
96+
97+
/* Copy the data segment initializers from flash to SRAM */
98+
INIT_DATA _sdata, _edata, _sidata
99+
100+
/* Zero fill the bss segments. */
101+
INIT_BSS _sbss, _ebss
102+
INIT_BSS _sMB_MEM2, _eMB_MEM2
85103

86104
/* Call the clock system intitialization function.*/
87105
bl SystemInit

‎system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
* STM32L1: 2.3.0
1414
* STM32L4: 1.5.1
1515
* STM32MP1: 1.1.0
16-
* STM32WB: 1.2.0
16+
* STM32WB: 1.3.0
1717

1818
Release notes of each STM32YYxx CMSIS available here:
1919

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