x86: fix cache ids on Intel

Use the official way to compute the cache id on Intel
(same one as in the Linux kernel) by rounding-up
nbthreads_sharing and masking lower bits of the APIC ids
(instead of dividing the APIC id by nbthreads_sharing).

This should not affect any existing platform topology,
but it's more future-proof.

Thanks to Jonathan Peyton for the help.

Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>

Author: bgoglin

hwloc/topology-x86.c

@@ -1,5 +1,5 @@
 /*
- * Copyright © 2010-2019 Inria.  All rights reserved.
+ * Copyright © 2010-2020 Inria.  All rights reserved.
  * Copyright © 2010-2013 Université Bordeaux
  * Copyright © 2010-2011 Cisco Systems, Inc.  All rights reserved.
  * See COPYING in top-level directory.
@@ -751,7 +751,13 @@ static void look_proc(struct hwloc_backend *backend, struct procinfo *infos, uns
     /* default cacheid value */
     cache->cacheid = infos->apicid / cache->nbthreads_sharing;
 
-    if (cpuid_type == amd) {
+    if (cpuid_type == intel) {
+      /* round nbthreads_sharing to nearest power of two to build a mask (for clearing lower bits) */
+      unsigned bits = hwloc_flsl(cache->nbthreads_sharing-1)+1;
+      unsigned mask = ~((1U<<(bits-1)) - 1);
+      cache->cacheid = infos->apicid & mask;
+
+    } else if (cpuid_type == amd) {
       /* AMD quirks */
       if (infos->cpufamilynumber == 0x17
 	  && cache->level == 3 && cache->nbthreads_sharing == 6) {