x86/microcode: Fix Entrysign revision check for Zen1/Naples

andyhhp · bp3tk0v · commit 876f0d43af78 · 2025-10-21T12:16:51.000+02:00
... to match AMD's statement here: https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7033.html Fixes: 50cef76 ("x86/microcode/AMD: Load only SHA256-checksummed patches") Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: <stable@kernel.org> Link: https://patch.msgid.link/20251020144124.2930784-1-andrew.cooper3@citrix.com
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
@@ -194,7 +194,7 @@ static bool need_sha_check(u32 cur_rev)
 	}
 
 	switch (cur_rev >> 8) {
-	case 0x80012: return cur_rev <= 0x800126f; break;
+	case 0x80012: return cur_rev <= 0x8001277; break;
 	case 0x80082: return cur_rev <= 0x800820f; break;
 	case 0x83010: return cur_rev <= 0x830107c; break;
 	case 0x86001: return cur_rev <= 0x860010e; break;

Original file line number	Diff line number	Diff line change
`@@ -194,7 +194,7 @@ static bool need_sha_check(u32 cur_rev)`
`194`	`194`	`}`
`195`	`195`
`196`	`196`	`switch (cur_rev >> 8) {`
`197`		`- case 0x80012: return cur_rev <= 0x800126f; break;`
	`197`	`+ case 0x80012: return cur_rev <= 0x8001277; break;`
`198`	`198`	`case 0x80082: return cur_rev <= 0x800820f; break;`
`199`	`199`	`case 0x83010: return cur_rev <= 0x830107c; break;`
`200`	`200`	`case 0x86001: return cur_rev <= 0x860010e; break;`