Merge branch 'master' of ssh://github.com/netwide-assembler/nasm

Author: H. Peter Anvin

asm/assemble.c

@@ -934,8 +934,12 @@ int64_t assemble(int32_t segment, int64_t start, int bits, insn *instruction)
                 nasm_nonfatal("instruction not supported in %d-bit mode", bits);
                 break;
             case MERR_ENCMISMATCH:
-                nasm_nonfatal("instruction not encodable with %s prefix",
-                              prefix_name(instruction->prefixes[PPS_REX]));
+                if (!instruction->prefixes[PPS_REX]) {
+                    nasm_nonfatal("instruction not encodable without explicit prefix");
+                } else {
+                    nasm_nonfatal("instruction not encodable with %s prefix",
+                                  prefix_name(instruction->prefixes[PPS_REX]));
+                }
                 break;
             case MERR_BADBND:
             case MERR_BADREPNE:
@@ -2552,6 +2556,17 @@ static enum match_result matches(const struct itemplate *itemp,
             return MERR_ENCMISMATCH;
         break;
     default:
+        if (itemp_has(itemp, IF_EVEX)) {
+            if (!iflag_test(&cpu, IF_EVEX))
+                return MERR_ENCMISMATCH;
+        } else if (itemp_has(itemp, IF_VEX)) {
+            if (!iflag_test(&cpu, IF_VEX)) {
+                return MERR_ENCMISMATCH;
+            } else if (itemp_has(itemp, IF_LATEVEX)) {
+                if (!iflag_test(&cpu, IF_LATEVEX) && iflag_test(&cpu, IF_EVEX))
+                    return MERR_ENCMISMATCH;
+            }
+        }
         break;
     }
 

asm/assemble.h

@@ -41,7 +41,9 @@
 #include "nasm.h"
 #include "iflag.h"
 
-extern iflag_t cpu;
+extern iflag_t cpu, cmd_cpu;
+void set_cpu(const char *cpuspec);
+
 extern bool in_absolute;        /* Are we in an absolute segment? */
 extern struct location absolute;
 

asm/directiv.c

@@ -1,6 +1,6 @@
 /* ----------------------------------------------------------------------- *
  *
- *   Copyright 1996-2019 The NASM Authors - All Rights Reserved
+ *   Copyright 1996-2022 The NASM Authors - All Rights Reserved
  *   See the file AUTHORS included with the NASM distribution for
  *   the specific copyright holders.
  *
@@ -59,11 +59,25 @@ struct cpunames {
     /* Eventually a table of features */
 };
 
-static iflag_t get_cpu(const char *value)
+static void iflag_set_cpu(iflag_t *a, unsigned int lvl)
 {
-    iflag_t r;
-    const struct cpunames *cpu;
+    a->field[0] = 0;     /* Not applicable to the CPU type */
+    iflag_set_all_features(a);    /* All feature masking bits set for now */
+    if (lvl >= IF_ANY) {
+        /* This is a hack for now */
+        iflag_set(a, IF_LATEVEX);
+    }
+    a->field[IF_CPU_FIELD] &= ~IF_CPU_LEVEL_MASK;
+    iflag_set(a, lvl);
+}
+
+void set_cpu(const char *value)
+{
+    const char *p;
+    char modifier;
+    const struct cpunames *cpuflag;
     static const struct cpunames cpunames[] = {
+        { "default", IF_DEFAULT }, /* Must be first */
         { "8086", IF_8086 },
         { "186",  IF_186  },
         { "286",  IF_286  },
@@ -96,22 +110,71 @@ static iflag_t get_cpu(const char *value)
         { "ivybridge", IF_FUTURE },
         { "any", IF_ANY },
         { "all", IF_ANY },
-        { "default", IF_PLEVEL },
-        { NULL, IF_PLEVEL }     /* Error and final default entry */
+        { "latevex", IF_LATEVEX },
+        { "evex", IF_EVEX },
+        { "vex", IF_VEX },
+        { NULL, 0 }
     };
 
-    iflag_clear_all(&r);
-
-    for (cpu = cpunames; cpu->name; cpu++) {
-        if (!nasm_stricmp(value, cpu->name))
-            break;
+    if (!value) {
+        iflag_set_cpu(&cpu, cpunames[0].level);
+        return;
     }
 
-    if (!cpu->name)
-        nasm_nonfatal("unknown 'cpu' type '%s'", value);
+    p = value;
+    modifier = '+';
+    while (*p) {
+        int len = strcspn(p, " ,");
+
+        while (len && (*p == '+' || *p == '-' || *p == '*')) {
+            modifier = *p++;
+            len--;
+            if (!len && modifier == '*')
+                cpu = cmd_cpu;
+        }
+
+        if (len) {
+            bool invert_flag = false;
+
+            if (len >= 3 && !nasm_memicmp(p, "no", 2)) {
+                invert_flag = true;
+                p += 2;
+                len -= 2;
+            }
 
-    iflag_set_cpu(&r, cpu->level);
-    return r;
+            for (cpuflag = cpunames; cpuflag->name; cpuflag++)
+                if (!nasm_strnicmp(p, cpuflag->name, len))
+                    break;
+
+            if (!cpuflag->name) {
+                nasm_nonfatal("unknown CPU type or flag '%.*s'", len, p);
+                return;
+            }
+
+            if (cpuflag->level >= IF_CPU_FIRST && cpuflag->level <= IF_ANY) {
+                iflag_set_cpu(&cpu, cpuflag->level);
+            } else {
+                switch (modifier) {
+                case '-':
+                    invert_flag = !invert_flag;
+                    break;
+                case '*':
+                    invert_flag ^= iflag_test(&cmd_cpu, cpuflag->level);
+                    break;
+                default:
+                    break;
+                }
+
+                iflag_set(&cpu, cpuflag->level);
+                if (invert_flag)
+                    iflag_clear(&cpu, cpuflag->level);
+            }
+        }
+        p += len;
+        if (!*p)
+            break;
+        p++;                /* Skip separator */
+    }
 }
 
 static int get_bits(const char *value)
@@ -358,11 +421,11 @@ bool process_directives(char *directive)
 
         if (!declare_label(value, type, special))
             break;
-        
+
         if (type == LBL_COMMON || type == LBL_EXTERN || type == LBL_REQUIRED)
             define_label(value, 0, size, false);
 
-    	break;
+	break;
     }
 
     case D_ABSOLUTE:        /* [ABSOLUTE address] */
@@ -440,7 +503,7 @@ bool process_directives(char *directive)
         break;
 
     case D_CPU:         /* [CPU] */
-        cpu = get_cpu(value);
+        set_cpu(value);
         break;
 
     case D_LIST:        /* [LIST {+|-}] */

asm/nasm.c

@@ -131,8 +131,7 @@ struct optimization optimizing =
     { MAX_OPTIMIZE, OPTIM_ALL_ENABLED }; /* number of optimization passes to take */
 static int cmd_sb = 16;    /* by default */
 
-iflag_t cpu;
-static iflag_t cmd_cpu;
+iflag_t cpu, cmd_cpu;
 
 struct location location;
 bool in_absolute;                 /* Flag we are in ABSOLUTE seg */
@@ -525,8 +524,8 @@ int main(int argc, char **argv)
 
     timestamp();
 
-    iflag_set_default_cpu(&cpu);
-    iflag_set_default_cpu(&cmd_cpu);
+    set_cpu(NULL);
+    cmd_cpu = cpu;
 
     set_default_limits();
 

doc/changes.src

@@ -68,6 +68,20 @@ reservations (e.g. \c{dw ?}.)
 \b Allow forcing an instruction in 64-bit mode to have a (possibly
 redundant) REX prefix, using the syntax \i\c{\{rex\}} as a prefix.
 
+\b Add a \c{\{vex\}} prefix to enforce VEX (AVX) encoding of an
+instruction, either using the 2- or 3-byte VEX prefixes.
+
+\b The \c{CPU} directive has been augmented to allow control of
+generation of VEX (AVX) versus EVEX (AVX-512) instruction formats, see
+\k{CPU}.
+
+\b Some recent instructions that previously have been only available
+using EVEX encodings are now also encodable using VEX (AVX)
+encodings. For backwards compatibility these encodings are not enabled
+by default, but can be generated either via an explicit \c{\{vex\}}
+prefix or by specifying either \c{CPU LATEVEX} or \c{CPU NOEVEX}; see
+\k{CPU}.
+
 \b Document the already existing \c{%unimacro} directive. See \k{unmacro}.
 
 \b Fix a code range generation bug in the DWARF debug format
@@ -76,6 +90,10 @@ output formats. This bug happened to cancel out with a bug in older
 versions of the GNU binutils linker, but breaks with other linkers and
 updated or other linkers that expect the spec to be followed.
 
+\b Fix segment symbols with addends, e.g. \c{jmp _TEXT+10h:0} in
+output formats that support segment relocations, e.g. the \c{obj}
+format.
+
 \b Fix various crashes and hangs on invalid input.
 
 
@@ -767,9 +785,10 @@ options to indicate whether all relevant branches should be getting
 \c{BND} prefixes.  This is expected to be the normal for use in MPX
 code.
 
-\b Add \c{{evex}}, \c{{vex3}} and \c{{vex2}} instruction prefixes to
-have NASM encode the corresponding instruction, if possible, with an EVEX,
-3-byte VEX, or 2-byte VEX prefix, respectively.
+\b Add \c{\{evex\}}, \c{\{vex3\}} and \c{\{vex2\}} instruction
+prefixes to have NASM encode the corresponding instruction, if
+possible, with an EVEX, 3-byte VEX, or 2-byte VEX prefix,
+respectively.
 
 \b Support for section names longer than 8 bytes in Win32/Win64 COFF.
 

doc/nasmdoc.src

@@ -5594,47 +5594,87 @@ are excluded from the symbol mangling and also not marked as global.
 \H{CPU} \i\c{CPU}: Defining CPU Dependencies
 
 The \i\c{CPU} directive restricts assembly to those instructions which
-are available on the specified CPU.
+are available on the specified CPU. At the moment, it is primarily
+used to enforce unavailable \e{encodings} of instructions, such as
+5-byte jumps on the 8080.
 
-Options are:
+(If someone would volunteer to work through the database and add
+proper annotations to each instruction, this could be greatly
+improved. Please contact the developers to volunteer, see \{contact}.)
 
-\b\c{CPU 8086}          Assemble only 8086 instruction set
+Current CPU keywords are:
 
-\b\c{CPU 186}           Assemble instructions up to the 80186 instruction set
+\b\c{CPU 8086}        - Assemble only 8086 instruction set
 
-\b\c{CPU 286}           Assemble instructions up to the 286 instruction set
+\b\c{CPU 186}         - Assemble instructions up to the 80186 instruction set
 
-\b\c{CPU 386}           Assemble instructions up to the 386 instruction set
+\b\c{CPU 286}         - Assemble instructions up to the 286 instruction set
 
-\b\c{CPU 486}           486 instruction set
+\b\c{CPU 386}         - Assemble instructions up to the 386 instruction set
 
-\b\c{CPU 586}           Pentium instruction set
+\b\c{CPU 486}         - 486 instruction set
 
-\b\c{CPU PENTIUM}       Same as 586
+\b\c{CPU 586}         - Pentium instruction set
 
-\b\c{CPU 686}           P6 instruction set
+\b\c{CPU PENTIUM}     - Same as 586
 
-\b\c{CPU PPRO}          Same as 686
+\b\c{CPU 686}         - P6 instruction set
 
-\b\c{CPU P2}            Same as 686
+\b\c{CPU PPRO}        - Same as 686
 
-\b\c{CPU P3}            Pentium III (Katmai) instruction sets
+\b\c{CPU P2}          - Same as 686
 
-\b\c{CPU KATMAI}        Same as P3
+\b\c{CPU P3}          - Pentium III (Katmai) instruction sets
 
-\b\c{CPU P4}            Pentium 4 (Willamette) instruction set
+\b\c{CPU KATMAI}      - Same as P3
 
-\b\c{CPU WILLAMETTE}    Same as P4
+\b\c{CPU P4}          - Pentium 4 (Willamette) instruction set
 
-\b\c{CPU PRESCOTT}      Prescott instruction set
+\b\c{CPU WILLAMETTE}  - Same as P4
 
-\b\c{CPU X64}           x86-64 (x64/AMD64/Intel 64) instruction set
+\b\c{CPU PRESCOTT}    - Prescott instruction set
 
-\b\c{CPU IA64}          IA64 CPU (in x86 mode) instruction set
+\b\c{CPU X64}         - x86-64 (x64/AMD64/Intel 64) instruction set
 
-All options are case insensitive.  All instructions will be selected
-only if they apply to the selected CPU or lower.  By default, all
-instructions are available.
+\b\c{CPU IA64}        - IA64 CPU (in x86 mode) instruction set
+
+\b\c{CPU DEFAULT}     - All available instructions
+
+\b\c{CPU ALL}	      - All available instructions \e{and flags}
+
+All options are case insensitive.
+
+In addition, optional flags can be specified to modify the instruction
+selections. These can be combined with a CPU declaration or specified
+alone. They can be prefixed by \c{+} (add flag, default), \c{-}
+(remove flag) or \c{*} (set flag to default); these prefixes are
+"sticky", so:
+
+\c      cpu -foo,bar
+
+means remove both the \c{foo} and \c{bar} options.
+
+If prefixed with \c{no}, it inverts the meaning of the flag, but this
+is not sticky, so:
+
+\c      cpu nofoo,bar
+
+means remove the \c{foo} flag but add the \c{bar} flag.
+
+Currently available flags are:
+
+\b\c{EVEX} - Enable generation of EVEX (AVX-512) encoded instructions
+without an explicit \c{\{evex\}} prefix. Default on.
+
+\b\c\{VEX} - Enable generation of VEX (AVX) or XOP encoded
+instructions without an explict \c{\{vex\}} prefix. Default on.
+
+\b\c{LATEVEX} - Enable generation of VEX (AVX) encoding of
+instructions where the VEX instructions forms were introduced
+\e{after} the corresponding EVEX (AVX-512) instruction forms without
+requiring an explicit \c{\{vex\}} prefix. This is implicit if the
+\c{EVEX} flag is disabled and the \c{VEX} flag is enabled. Default
+off.
 
 
 \H{FLOAT} \i\c{FLOAT}: Handling of \I{floating-point, constants}floating-point constants
@@ -5643,19 +5683,19 @@ By default, floating-point constants are rounded to nearest, and IEEE
 denormals are supported.  The following options can be set to alter
 this behaviour:
 
-\b\c{FLOAT DAZ}         Flush denormals to zero
+\b\c{FLOAT DAZ}       - Flush denormals to zero
 
-\b\c{FLOAT NODAZ}       Do not flush denormals to zero (default)
+\b\c{FLOAT NODAZ}     - Do not flush denormals to zero (default)
 
-\b\c{FLOAT NEAR}        Round to nearest (default)
+\b\c{FLOAT NEAR}      - Round to nearest (default)
 
-\b\c{FLOAT UP}          Round up (toward +Infinity)
+\b\c{FLOAT UP}        - Round up (toward +Infinity)
 
-\b\c{FLOAT DOWN}        Round down (toward -Infinity)
+\b\c{FLOAT DOWN}      - Round down (toward -Infinity)
 
-\b\c{FLOAT ZERO}        Round toward zero
+\b\c{FLOAT ZERO}      - Round toward zero
 
-\b\c{FLOAT DEFAULT}     Restore default settings
+\b\c{FLOAT DEFAULT}   - Restore default settings
 
 The standard macros \i\c{__?FLOAT_DAZ?__}, \i\c{__?FLOAT_ROUND?__}, and
 \i\c{__?FLOAT?__} contain the current state, as long as the programmer