Merge pull request #84 from mythril-hypervisor/adam-dev

General interrupt and IO implementation

Author: ALSchwalm

linux

@@ -11,6 +11,7 @@ description = "A intel-focused hypervisor using VT-x/EPT"
 test = []
 
 [dependencies]
+arraydeque = { version = "0.4.5", default-features = false }
 arrayvec = { version = "0.5.1", default-features = false }
 bitflags = "1.2.0"
 byteorder = { version = "1", default-features = false }
@@ -25,7 +26,7 @@ spin = "0.5"
 ux = { version = "0.1.3", default-features = false }
 
 [dependencies.iced-x86]
-version = "1.1.0"
+version = "1.8.0"
 default-features = false
 features = ["no_std", "decoder"]
 

mythril/Cargo.lock

@@ -6,6 +6,8 @@ use crate::{declare_per_core, get_per_core, get_per_core_mut};
 use raw_cpuid::CpuId;
 use x86::msr;
 
+use core::fmt;
+
 /// APIC base physical address mask.
 const IA32_APIC_BASE_MASK: u64 = 0xffff_f000;
 /// xAPIC global enable mask
@@ -103,6 +105,33 @@ pub unsafe fn get_local_apic_mut() -> &'static mut LocalApic {
         .expect("Attempt to get local APIC before initialization")
 }
 
+/// A representation of a APIC ID
+#[derive(Copy, Clone, Debug, Ord, PartialEq, PartialOrd, Eq)]
+pub struct ApicId {
+    /// The raw ID as an integer
+    pub raw: u32,
+}
+
+impl ApicId {
+    /// Returns whether this is the BSP core
+    pub fn is_bsp(&self) -> bool {
+        //TODO(alschwalm): This is not correct for multi socket systems
+        self.raw == 0
+    }
+}
+
+impl From<u32> for ApicId {
+    fn from(value: u32) -> Self {
+        ApicId { raw: value }
+    }
+}
+
+impl fmt::Display for ApicId {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "0x{:x}", self.raw)
+    }
+}
+
 /// Structure defining the interface for a local x2APIC
 #[derive(Debug)]
 pub struct LocalApic {
@@ -188,8 +217,10 @@ impl LocalApic {
     }
 
     /// The APIC ID
-    pub fn id(&self) -> usize {
-        unsafe { msr::rdmsr(msr::IA32_X2APIC_APICID) as usize }
+    pub fn id(&self) -> ApicId {
+        ApicId {
+            raw: unsafe { msr::rdmsr(msr::IA32_X2APIC_APICID) as u32 },
+        }
     }
 
     /// The Logical APIC ID
@@ -249,15 +280,15 @@ impl LocalApic {
     /// Set the Interrupt Command Register
     pub fn send_ipi(
         &mut self,
-        dst: u32,
+        dst: ApicId,
         dst_short: DstShorthand,
         trigger: TriggerMode,
         level: Level,
         dst_mode: DstMode,
         delivery_mode: DeliveryMode,
         vector: u8,
     ) {
-        let mut icr: u64 = (dst as u64) << 32;
+        let mut icr: u64 = (dst.raw as u64) << 32;
         icr |= (dst_short as u64) << 18;
         icr |= (trigger as u64) << 15;
         icr |= (level as u64) << 14;

mythril/Cargo.toml

@@ -148,10 +148,36 @@ _start:
     call map_page_directory
     pop edi
 
-    ; Disable IRQs (probably not necessary)
-    mov al, 0xFF                      ; Out 0xFF to 0xA1 and 0x21 to disable all IRQs.
-    out 0xA1, al
+    ; Setup PIC
+    mov al, 0x11
+    out 0x20, al
+    out 0xa0, al
+
+    ; Setup offsets
+    mov al, 0x20
+    out 0x21, al
+    mov al, 0x28
+    out 0xa1, al
+
+    mov al, 0x4
+    out 0x21, al
+    mov al, 0x2
+    out 0xa1, al
+
+    mov al, 0x1
+    out 0x21, al
+    out 0xa1, al
+
+    ;; Mask everything so the I/O APIC will work
+    mov al, 0xff
     out 0x21, al
+    mov al, 0xff
+    out 0xA1, al
+
+    ;; ACK any pending interrupts
+    mov al, 0x20
+    out 0x20, al
+    out 0xa0, al
 
     ; Enter long mode.
     mov eax, 10100000b                ; Set the PAE and PGE bit.