Merge pull request #107 from mythril-hypervisor/multi-core-guest

Multi core guest support

Author: dlrobertson

.github/workflows/rust.yml

@@ -6,7 +6,7 @@ jobs:
   fmt:
     runs-on: ubuntu-18.04
     container:
-      image: adamschwalm/hypervisor-build:14
+      image: adamschwalm/hypervisor-build:16
       options: "-u 0:0"
     steps:
     - uses: actions/checkout@v1
@@ -17,7 +17,7 @@ jobs:
     runs-on: ubuntu-18.04
     needs: fmt
     container:
-      image: adamschwalm/hypervisor-build:14
+      image: adamschwalm/hypervisor-build:16
       options: "-u 0:0"
     steps:
     - uses: actions/checkout@v1
@@ -30,7 +30,7 @@ jobs:
     runs-on: ubuntu-18.04
     needs: fmt
     container:
-      image: adamschwalm/hypervisor-build:14
+      image: adamschwalm/hypervisor-build:16
       options: "-u 0:0"
     steps:
     - uses: actions/checkout@v1

Makefile

@@ -1,6 +1,6 @@
 CARGO?=cargo
 BUILD_TYPE?=release
-BUILD_REPO_TAG=14
+BUILD_REPO_TAG=16
 DOCKER_IMAGE=adamschwalm/hypervisor-build:$(BUILD_REPO_TAG)
 
 TEST_IMAGE_REPO=https://github.com/mythril-hypervisor/build

mythril/Cargo.lock

@@ -17,7 +17,7 @@ bitflags = "1.2.0"
 byteorder = { version = "1", default-features = false }
 num_enum = { version = "0.5.0", default-features = false }
 x86 = "0.34.0"
-linked_list_allocator = "0.8.1"
+linked_list_allocator = "0.8.6"
 log = { version = "0.4.8", default-features = false }
 multiboot = "0.3.0"
 multiboot2 = "0.9.0"

mythril/Cargo.toml

@@ -56,6 +56,9 @@ ap_startup_32:
     mov ds, ax
     mov ss, ax
     mov es, ax
+
+    ; Ensure FS/GS are zeroed
+    xor ax, ax
     mov fs, ax
     mov gs, ax
 
@@ -88,12 +91,6 @@ ap_startup_64:
     ; Load the stack provided by the bsp
     mov rsp, [AP_STACK_ADDR]
 
-    ; Initialize FS with our per-core index, this will be used for the
-    ; fast per-core access later
-    mov rdx, [AP_IDX]
-    shl rdx, 3          ; Shift the AP_IDX to allow the RPL and TI bits to be 0
-    mov fs, rdx
-
     ; See ap::ApData
     push qword [AP_IDX]
 

mythril/src/ap_startup.S

@@ -3,6 +3,7 @@
 use crate::error::{Error, Result};
 use crate::time;
 use crate::{declare_per_core, get_per_core, get_per_core_mut};
+use num_enum::TryFromPrimitive;
 use raw_cpuid::CpuId;
 use x86::msr;
 
@@ -17,21 +18,21 @@ const IA32_APIC_BASE_EXD: u64 = 1 << 10;
 /// BSP mask
 const IA32_APIC_BASE_BSP: u64 = 1 << 8;
 
-#[derive(Debug)]
+#[derive(Debug, TryFromPrimitive)]
 #[repr(u8)]
 /// ICR destination shorthand values
 pub enum DstShorthand {
     /// No shorthand used
     NoShorthand = 0x00,
-    // TODO(dlrobertson): Is there any reason to include self? AFAIK
-    // SELF_IPI negates the need for it.
+    /// Send only to myself
+    MySelf = 0x01,
     /// Broadcast including myself
     AllIncludingSelf = 0x02,
     /// Broadcast excluding myself
     AllExcludingSelf = 0x03,
 }
 
-#[derive(Debug)]
+#[derive(Debug, TryFromPrimitive)]
 #[repr(u8)]
 /// INIT IPI Level
 pub enum Level {
@@ -41,7 +42,7 @@ pub enum Level {
     Assert = 0x01,
 }
 
-#[derive(Debug)]
+#[derive(Debug, TryFromPrimitive)]
 #[repr(u8)]
 /// ICR trigger modes
 pub enum TriggerMode {
@@ -51,7 +52,7 @@ pub enum TriggerMode {
     Level = 0x01,
 }
 
-#[derive(Debug)]
+#[derive(Debug, TryFromPrimitive)]
 #[repr(u8)]
 /// ICR mode of the Destination field
 pub enum DstMode {
@@ -61,7 +62,7 @@ pub enum DstMode {
     Logical = 0x01,
 }
 
-#[derive(Debug)]
+#[derive(Debug, TryFromPrimitive)]
 #[repr(u8)]
 /// ICR delivery mode
 pub enum DeliveryMode {

mythril/src/apic.rs

@@ -227,11 +227,11 @@ trampoline:
     mov eax, GDT64.data
     mov ds, eax
     mov es, eax
-    mov gs, eax
     mov ss, eax
 
-    ; FS stores the per-core index, which is always 0 for the BSP
-    mov edx, 0
+    ; Ensure GS/FS are zeroed
+    xor edx, edx
+    mov gs, edx
     mov fs, edx
 
     jmp kmain_early