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folkertdevAmanieu
folkertdev
authored and
Amanieu
committed
shorten array literals
1 parent 704d7a7 commit bb6a3a5

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2 files changed

+28
-104
lines changed

2 files changed

+28
-104
lines changed

‎stdarch/crates/core_arch/src/arm_shared/neon/generated.rs‎

Lines changed: 14 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -40758,16 +40758,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
4075840758
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")]
4075940759
fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
4076040760
}
40761-
unsafe {
40762-
_vqshlu_n_s8(
40763-
a,
40764-
const {
40765-
int8x8_t([
40766-
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40767-
])
40768-
},
40769-
)
40770-
}
40761+
unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) }
4077140762
}
4077240763
#[doc = "Signed saturating shift left unsigned"]
4077340764
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
@@ -40783,17 +40774,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
4078340774
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")]
4078440775
fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
4078540776
}
40786-
unsafe {
40787-
_vqshluq_n_s8(
40788-
a,
40789-
const {
40790-
int8x16_t([
40791-
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40792-
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40793-
])
40794-
},
40795-
)
40796-
}
40777+
unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) }
4079740778
}
4079840779
#[doc = "Signed saturating shift left unsigned"]
4079940780
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
@@ -40809,12 +40790,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
4080940790
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")]
4081040791
fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
4081140792
}
40812-
unsafe {
40813-
_vqshlu_n_s16(
40814-
a,
40815-
const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
40816-
)
40817-
}
40793+
unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) }
4081840794
}
4081940795
#[doc = "Signed saturating shift left unsigned"]
4082040796
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
@@ -40830,16 +40806,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
4083040806
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")]
4083140807
fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
4083240808
}
40833-
unsafe {
40834-
_vqshluq_n_s16(
40835-
a,
40836-
const {
40837-
int16x8_t([
40838-
N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
40839-
])
40840-
},
40841-
)
40842-
}
40809+
unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) }
4084340810
}
4084440811
#[doc = "Signed saturating shift left unsigned"]
4084540812
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
@@ -40855,7 +40822,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
4085540822
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")]
4085640823
fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
4085740824
}
40858-
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
40825+
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) }
4085940826
}
4086040827
#[doc = "Signed saturating shift left unsigned"]
4086140828
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
@@ -40871,12 +40838,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
4087140838
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")]
4087240839
fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
4087340840
}
40874-
unsafe {
40875-
_vqshluq_n_s32(
40876-
a,
40877-
const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
40878-
)
40879-
}
40841+
unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) }
4088040842
}
4088140843
#[doc = "Signed saturating shift left unsigned"]
4088240844
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
@@ -40908,7 +40870,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
4090840870
#[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")]
4090940871
fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
4091040872
}
40911-
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
40873+
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) }
4091240874
}
4091340875
#[doc = "Signed saturating shift left unsigned"]
4091440876
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"]
@@ -40927,16 +40889,7 @@ pub fn vqshlu_n_s8<const N: i32>(a: int8x8_t) -> uint8x8_t {
4092740889
)]
4092840890
fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> uint8x8_t;
4092940891
}
40930-
unsafe {
40931-
_vqshlu_n_s8(
40932-
a,
40933-
const {
40934-
int8x8_t([
40935-
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40936-
])
40937-
},
40938-
)
40939-
}
40892+
unsafe { _vqshlu_n_s8(a, const { int8x8_t([N as i8; 8]) }) }
4094040893
}
4094140894
#[doc = "Signed saturating shift left unsigned"]
4094240895
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"]
@@ -40955,17 +40908,7 @@ pub fn vqshluq_n_s8<const N: i32>(a: int8x16_t) -> uint8x16_t {
4095540908
)]
4095640909
fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> uint8x16_t;
4095740910
}
40958-
unsafe {
40959-
_vqshluq_n_s8(
40960-
a,
40961-
const {
40962-
int8x16_t([
40963-
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40964-
N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8,
40965-
])
40966-
},
40967-
)
40968-
}
40911+
unsafe { _vqshluq_n_s8(a, const { int8x16_t([N as i8; 16]) }) }
4096940912
}
4097040913
#[doc = "Signed saturating shift left unsigned"]
4097140914
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"]
@@ -40984,12 +40927,7 @@ pub fn vqshlu_n_s16<const N: i32>(a: int16x4_t) -> uint16x4_t {
4098440927
)]
4098540928
fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> uint16x4_t;
4098640929
}
40987-
unsafe {
40988-
_vqshlu_n_s16(
40989-
a,
40990-
const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) },
40991-
)
40992-
}
40930+
unsafe { _vqshlu_n_s16(a, const { int16x4_t([N as i16; 4]) }) }
4099340931
}
4099440932
#[doc = "Signed saturating shift left unsigned"]
4099540933
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"]
@@ -41008,16 +40946,7 @@ pub fn vqshluq_n_s16<const N: i32>(a: int16x8_t) -> uint16x8_t {
4100840946
)]
4100940947
fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> uint16x8_t;
4101040948
}
41011-
unsafe {
41012-
_vqshluq_n_s16(
41013-
a,
41014-
const {
41015-
int16x8_t([
41016-
N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16,
41017-
])
41018-
},
41019-
)
41020-
}
40949+
unsafe { _vqshluq_n_s16(a, const { int16x8_t([N as i16; 8]) }) }
4102140950
}
4102240951
#[doc = "Signed saturating shift left unsigned"]
4102340952
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"]
@@ -41036,7 +40965,7 @@ pub fn vqshlu_n_s32<const N: i32>(a: int32x2_t) -> uint32x2_t {
4103640965
)]
4103740966
fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> uint32x2_t;
4103840967
}
41039-
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }) }
40968+
unsafe { _vqshlu_n_s32(a, const { int32x2_t([N; 2]) }) }
4104040969
}
4104140970
#[doc = "Signed saturating shift left unsigned"]
4104240971
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"]
@@ -41055,12 +40984,7 @@ pub fn vqshluq_n_s32<const N: i32>(a: int32x4_t) -> uint32x4_t {
4105540984
)]
4105640985
fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> uint32x4_t;
4105740986
}
41058-
unsafe {
41059-
_vqshluq_n_s32(
41060-
a,
41061-
const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) },
41062-
)
41063-
}
40987+
unsafe { _vqshluq_n_s32(a, const { int32x4_t([N; 4]) }) }
4106440988
}
4106540989
#[doc = "Signed saturating shift left unsigned"]
4106640990
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"]
@@ -41098,7 +41022,7 @@ pub fn vqshluq_n_s64<const N: i32>(a: int64x2_t) -> uint64x2_t {
4109841022
)]
4109941023
fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> uint64x2_t;
4110041024
}
41101-
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }) }
41025+
unsafe { _vqshluq_n_s64(a, const { int64x2_t([N as i64; 2]) }) }
4110241026
}
4110341027
#[doc = "Signed saturating shift right narrow"]
4110441028
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]

‎stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -11447,14 +11447,14 @@ intrinsics:
1144711447
static_defs: ['const N: i32']
1144811448
safety: safe
1144911449
types:
11450-
- [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }']
11451-
- [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }']
11452-
- [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N as i32, N as i32]) }']
11450+
- [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8; 8]) }']
11451+
- [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16; 4]) }']
11452+
- [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N; 2]) }']
1145311453
- [int64x1_t, uint64x1_t, '6', 'const { int64x1_t([N as i64]) }']
11454-
- [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }']
11455-
- [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }']
11456-
- [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }']
11457-
- [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64, N as i64]) }']
11454+
- [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8; 16]) }']
11455+
- [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16; 8]) }']
11456+
- [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N; 4]) }']
11457+
- [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64; 2]) }']
1145811458
compose:
1145911459
- FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]]
1146011460
- LLVMLink:
@@ -11479,14 +11479,14 @@ intrinsics:
1147911479
static_defs: ['const N: i32']
1148011480
safety: safe
1148111481
types:
11482-
- [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }']
11483-
- [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }']
11484-
- [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N as i32, N as i32]) }']
11482+
- [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8; 8]) }']
11483+
- [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16; 4]) }']
11484+
- [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N; 2]) }']
1148511485
- [int64x1_t, uint64x1_t, '6', 'const { int64x1_t([N as i64]) }']
11486-
- [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }']
11487-
- [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }']
11488-
- [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }']
11489-
- [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64, N as i64]) }']
11486+
- [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8; 16]) }']
11487+
- [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16; 8]) }']
11488+
- [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N; 4]) }']
11489+
- [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64; 2]) }']
1149011490
compose:
1149111491
- FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]]
1149211492
- LLVMLink:

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