@@ -4,8 +4,6 @@ use crate::{
44 ptr,
55};
66
7-
8-
97#[cfg(test)]
108use stdarch_test::assert_instr;
119
@@ -11304,33 +11302,32 @@ pub fn _mm512_bsrli_epi128<const IMM8: i32>(a: __m512i) -> __m512i {
1130411302#[rustc_legacy_const_generics(2)]
1130511303pub fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
1130611304 const fn mask(shift: u32, i: u32) -> u32 {
11307- let shift = shift % 16;
11308- let mod_i = i%16;
11309- if mod_i < (16 - shift) {
11310- i + shift
11311- } else {
11312- i + 48 + shift
11313- }
11314- }
11315-
11316- // If palignr is shifting the pair of vectors more than the size of two
11317- // lanes, emit zero.
11318- if IMM8 >= 32 {
11319- return _mm512_setzero_si512();
11320- }
11321- // If palignr is shifting the pair of input vectors more than one lane,
11322- // but less than two lanes, convert to shifting in zeroes.
11323- let (a, b) = if IMM8 > 16 {
11324- (_mm512_setzero_si512(), a)
11305+ let shift = shift % 16;
11306+ let mod_i = i % 16;
11307+ if mod_i < (16 - shift) {
11308+ i + shift
1132511309 } else {
11326- (a, b)
11327- };
11310+ i + 48 + shift
11311+ }
11312+ }
11313+
11314+ // If palignr is shifting the pair of vectors more than the size of two
11315+ // lanes, emit zero.
11316+ if IMM8 >= 32 {
11317+ return _mm512_setzero_si512();
11318+ }
11319+ // If palignr is shifting the pair of input vectors more than one lane,
11320+ // but less than two lanes, convert to shifting in zeroes.
11321+ let (a, b) = if IMM8 > 16 {
11322+ (_mm512_setzero_si512(), a)
11323+ } else {
11324+ (a, b)
11325+ };
1132811326 unsafe {
1132911327 if IMM8 == 16 {
1133011328 return transmute(a);
1133111329 }
11332-
11333-
11330+
1133411331 let r: i8x64 = simd_shuffle!(
1133511332 b.as_i8x64(),
1133611333 a.as_i8x64(),
@@ -11351,7 +11348,7 @@ pub fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
1135111348 mask(IMM8 as u32, 13),
1135211349 mask(IMM8 as u32, 14),
1135311350 mask(IMM8 as u32, 15),
11354- mask(IMM8 as u32, 16),
11351+ mask(IMM8 as u32, 16),
1135511352 mask(IMM8 as u32, 17),
1135611353 mask(IMM8 as u32, 18),
1135711354 mask(IMM8 as u32, 19),
@@ -11367,7 +11364,7 @@ pub fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
1136711364 mask(IMM8 as u32, 29),
1136811365 mask(IMM8 as u32, 30),
1136911366 mask(IMM8 as u32, 31),
11370- mask(IMM8 as u32, 32),
11367+ mask(IMM8 as u32, 32),
1137111368 mask(IMM8 as u32, 33),
1137211369 mask(IMM8 as u32, 34),
1137311370 mask(IMM8 as u32, 35),
@@ -11383,7 +11380,7 @@ pub fn _mm512_alignr_epi8<const IMM8: i32>(a: __m512i, b: __m512i) -> __m512i {
1138311380 mask(IMM8 as u32, 45),
1138411381 mask(IMM8 as u32, 46),
1138511382 mask(IMM8 as u32, 47),
11386- mask(IMM8 as u32, 48),
11383+ mask(IMM8 as u32, 48),
1138711384 mask(IMM8 as u32, 49),
1138811385 mask(IMM8 as u32, 50),
1138911386 mask(IMM8 as u32, 51),
@@ -11493,7 +11490,7 @@ pub fn _mm_mask_alignr_epi8<const IMM8: i32>(
1149311490 a: __m128i,
1149411491 b: __m128i,
1149511492) -> __m128i {
11496- unsafe {`
11493+ unsafe {
1149711494 static_assert_uimm_bits!(IMM8, 8);
1149811495 let r = _mm_alignr_epi8::<IMM8>(a, b);
1149911496 transmute(simd_select_bitmask(k, r.as_i8x16(), src.as_i8x16()))
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