Merge pull request #24 from ThomasWaldmann/more-compat-tests

more compat tests

Author: ThomasWaldmann

demo.S

@@ -54,12 +54,12 @@ textend:
 data0:      .skip 4, 0x23
 data1:      .space 4, 0x42
 data2:      .skip 4
-datab:      .byte 1, 2, 3, 4
 dataw:      .word 1, 2, 3, 4
 datal:      .long 1, 2, 3, 4
+datab:      .byte 1, 2, 3  # test alignment / fill up of section
 dataend:
 
             .bss
 bss0:       .skip 4
-bss1:       .skip 2
+bss1:       .skip 2  # test alignment / fill up of section
 bssend:

esp32_ulp/assemble.py

@@ -65,6 +65,18 @@ def append_section(self, value, expected_section=None):
             self.sections[s].append(value)
             self.offsets[s] += len(value)
 
+    def finalize_sections(self):
+        # make sure all sections have a bytelength dividable by 4,
+        # thus having all sections aligned at 32bit-word boundaries.
+        for s in list(self.sections.keys()) + [BSS, ]:
+            offs = self.offsets[s]
+            mod = offs % 4
+            if mod:
+                fill = int(0).to_bytes(4 - mod, 'little')
+                self.offsets[s] += len(fill)
+                if s is not BSS:
+                    self.sections[s].append(fill)
+
     def dump(self):
         print("Symbols:")
         for label, section_offset in sorted(self.symbols.items()):
@@ -144,4 +156,5 @@ def assemble(self, lines):
                         self.append_section(instruction.to_bytes(4, 'little'), TEXT)
                         continue
                 raise Exception('Unknown opcode or directive: %s' % opcode)
+        self.finalize_sections()
 

esp32_ulp/opcodes.py

@@ -142,10 +142,10 @@ def make_ins(layout):
 
 
 _st = make_ins("""
-    dreg : 2        # Register which contains data to store
-    sreg : 2        # Register which contains address in RTC memory (expressed in words)
+    sreg : 2        # Register which contains data to store
+    dreg : 2        # Register which contains address in RTC memory (expressed in words)
     unused1 : 6     # Unused
-    offset : 11     # Offset to add to sreg
+    offset : 11     # Offset to add to dreg
     unused2 : 4     # Unused
     sub_opcode : 3  # Sub opcode (SUB_OPCODE_ST)
     opcode : 4      # Opcode (OPCODE_ST)
@@ -378,9 +378,9 @@ def i_wait(cycles):
     return _delay.all
 
 
-def i_adc(reg_dest, adc_idx, pad_idx):
+def i_adc(reg_dest, adc_idx, mux):
     _adc.dreg = get_reg(reg_dest)
-    _adc.mux = get_imm(pad_idx) + 1
+    _adc.mux = get_imm(mux)
     _adc.sar_sel = get_imm(adc_idx)
     _adc.unused1 = 0
     _adc.cycles = 0
@@ -390,10 +390,10 @@ def i_adc(reg_dest, adc_idx, pad_idx):
 
 
 def i_st(reg_val, reg_addr, offset):
-    _st.dreg = get_reg(reg_val)
-    _st.sreg = get_reg(reg_addr)
+    _st.dreg = get_reg(reg_addr)
+    _st.sreg = get_reg(reg_val)
     _st.unused1 = 0
-    _st.offset = get_imm(offset)
+    _st.offset = get_imm(offset) // 4
     _st.unused2 = 0
     _st.sub_opcode = SUB_OPCODE_ST
     _st.opcode = OPCODE_ST
@@ -410,7 +410,7 @@ def i_ld(reg_dest, reg_addr, offset):
     _ld.dreg = get_reg(reg_dest)
     _ld.sreg = get_reg(reg_addr)
     _ld.unused1 = 0
-    _ld.offset = get_imm(offset)
+    _ld.offset = get_imm(offset) // 4
     _ld.unused2 = 0
     _ld.opcode = OPCODE_LD
     return _ld.all
@@ -423,7 +423,7 @@ def i_move(reg_dest, reg_imm_src):
     if src.type == REG:
         _alu_reg.dreg = dest
         _alu_reg.sreg = src.value
-        _alu_reg.treg = 0
+        _alu_reg.treg = 1  # XXX undocumented, this is the value binutils-esp32 uses
         _alu_reg.unused = 0
         _alu_reg.sel = ALU_SEL_MOV
         _alu_reg.sub_opcode = SUB_OPCODE_ALU_REG

tests/compat/alu.S

@@ -18,4 +18,16 @@
             sub r3, r0, -1
             sub r2, r1, 1
 
+            lsh r0, r1, r2
+            lsh r2, r3, 1
+
+            rsh r3, r2, r1
+            rsh r3, r2, 31
+
+            move r0, r1
+            move r0, 42
+
+            stage_rst
+            stage_inc 42
+            stage_dec 23
 

tests/compat/io.S

@@ -0,0 +1,9 @@
+            .text
+
+            reg_rd 0x3ff48000, 7, 0
+            reg_wr 0x3ff48000, 7, 0, 42
+
+            i2c_rd 0x10, 7, 0, 0
+            i2c_wr 0x23, 0x42, 7, 0, 1
+
+            adc r0, 1, 2

tests/compat/memory.S

@@ -0,0 +1,8 @@
+            .text
+
+            ld r0, r1, 0
+            ld r2, r3, 4
+
+            st r0, r1, 0
+            st r3, r2, 8
+

tests/compat/sections.S

@@ -0,0 +1,15 @@
+            .text
+
+            nop
+            nop
+            nop
+
+            .data
+
+            .space 4
+            .space 8, 0xFF
+
+            .bss
+
+            .space 10
+

tests/compat/sleep.S

@@ -0,0 +1,9 @@
+            .text
+
+            nop
+            wait 1000
+
+            wake
+            sleep 1
+
+            halt