Fix esp32s2 ST instructions with label field

Specifying 0 as the label is different than not specifying a
label at all. This commit corrects the behaviour when label 0
is used.

Also run the all_opcodes fixture as integration test to ensure
the same result as binutils-gdb/esp32ulp-as (which is how this
bug was found).

Author: wnienhaus

esp32_ulp/opcodes_s2.py

@@ -491,12 +491,12 @@ def i_st_manual(reg_val, reg_addr, offset, label, upper, wr_way):
     return _st.all
 
 
-def i_stl(reg_val, reg_addr, offset, label="0"):
-    return i_st_manual(reg_val, reg_addr, offset, label, 0, 3 if label=="0" else 1)
+def i_stl(reg_val, reg_addr, offset, label=None):
+    return i_st_manual(reg_val, reg_addr, offset, label if label else "0", 0, 1 if label else 3)
 
 
-def i_sth(reg_val, reg_addr, offset, label="0"):
-    return i_st_manual(reg_val, reg_addr, offset, label, 1, 3 if label=="0" else 1)
+def i_sth(reg_val, reg_addr, offset, label=None):
+    return i_st_manual(reg_val, reg_addr, offset, label if label else "0", 1, 1 if label else 3)
 
 
 def i_st(reg_val, reg_addr, offset):
@@ -535,8 +535,8 @@ def i_sto(offset):
     return _st.all
 
 
-def i_sti(reg_val, reg_addr, label="0"):
-    return i_st_auto(reg_val, reg_addr, label, 3 if label=="0" else 1)
+def i_sti(reg_val, reg_addr, label=None):
+    return i_st_auto(reg_val, reg_addr, label if label else "0", 1 if label else 3)
 
 
 def i_sti32(reg_val, reg_addr, label):

tests/01_compat_tests.sh

@@ -14,7 +14,7 @@ run_tests_for_cpu() {
     local cpu=$1
     echo "Testing for CPU: $cpu"
 
-    for src_file in $(ls -1 compat/*.S); do
+    for src_file in $(ls -1 compat/*.S fixtures/*.S); do
         src_name="${src_file%.S}"
 
         # files with a cpu encoded into their name are only run for that cpu

tests/fixtures/all_opcodes-v.esp32s2.lst

@@ -384,7 +384,7 @@ ULP magic    : b'ulp\x00' (0x00706c75)
                  label      =   0
                  upper      =   0
                  wr_way     =   3
-00c0  89210068  ST r1, r2, 8
+00c0  89200068  ST r1, r2, 8
                  dreg       =   2
                  offset     =   8
                  opcode     =   6
@@ -394,7 +394,7 @@ ULP magic    : b'ulp\x00' (0x00706c75)
                  unused2    =   0
                  label      =   0
                  upper      =   0
-                 wr_way     =   3
+                 wr_way     =   1
 00c4  99200068  STL r1, r2, 8, 1
                  dreg       =   2
                  offset     =   8
@@ -417,7 +417,7 @@ ULP magic    : b'ulp\x00' (0x00706c75)
                  label      =   0
                  upper      =   1
                  wr_way     =   3
-00cc  c9210068  STH r1, r2, 8
+00cc  c9200068  STH r1, r2, 8
                  dreg       =   2
                  offset     =   8
                  opcode     =   6
@@ -427,7 +427,7 @@ ULP magic    : b'ulp\x00' (0x00706c75)
                  unused2    =   0
                  label      =   0
                  upper      =   1
-                 wr_way     =   3
+                 wr_way     =   1
 00d0  d9200068  STH r1, r2, 8, 1
                  dreg       =   2
                  offset     =   8
@@ -472,7 +472,7 @@ ULP magic    : b'ulp\x00' (0x00706c75)
                  label      =   0
                  upper      =   0
                  wr_way     =   3
-00e0  89010062  STI r1, r2
+00e0  89000062  STI r1, r2
                  dreg       =   2
                  offset     =   0
                  opcode     =   6
@@ -482,7 +482,7 @@ ULP magic    : b'ulp\x00' (0x00706c75)
                  unused2    =   0
                  label      =   0
                  upper      =   0
-                 wr_way     =   3
+                 wr_way     =   1
 00e4  99000062  STI r1, r2, 1
                  dreg       =   2
                  offset     =   0

tests/fixtures/all_opcodes.esp32s2.lst

@@ -47,15 +47,15 @@
 00b4  092000d0  LD r1, r2, 8
 00b8  092000d8  LDH r1, r2, 8
 00bc  89210068  ST r1, r2, 8
-00c0  89210068  ST r1, r2, 8
+00c0  89200068  ST r1, r2, 8
 00c4  99200068  STL r1, r2, 8, 1
 00c8  c9210068  STH r1, r2, 8
-00cc  c9210068  STH r1, r2, 8
+00cc  c9200068  STH r1, r2, 8
 00d0  d9200068  STH r1, r2, 8, 1
 00d4  09200068  ST32 r1, r2, 8, 0
 00d8  19200068  ST32 r1, r2, 8, 1
 00dc  89010062  STI r1, r2
-00e0  89010062  STI r1, r2
+00e0  89000062  STI r1, r2
 00e4  99000062  STI r1, r2, 1
 00e8  09000062  STI32 r1, r2, 0
 00ec  19000062  STI32 r1, r2, 1