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maksyukimaksyuki
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refactor: add ls inst io port class to format code
1 parent 605bcc5 commit 38c94d8

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9 files changed

+108
-138
lines changed

9 files changed

+108
-138
lines changed

‎rtl/tc_l2/src/main/scala/core/CSRReg.scala‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,10 @@ import treecorel2.common.ConstVal._
88
class CSRReg() extends Module with InstConfig {
99
val io = IO(new Bundle {
1010
// from id
11+
val inst: INSTIO = new INSTIO
1112
val rdAddrIn: UInt = Input(UInt(CSRAddrLen.W))
1213
val instOperTypeIn: UInt = Input(UInt(InstOperTypeLen.W))
13-
val inst: INSTIO = new INSTIO
14+
1415
// from ex's out
1516
val wtEnaIn: Bool = Input(Bool())
1617
val wtDataIn: UInt = Input(UInt(BusWidth.W))

‎rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala‎

Lines changed: 18 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -34,28 +34,24 @@ class TreeCoreL2() extends Module with AXI4Config with InstConfig {
3434
if2id.io.instIn.addr := pcUnit.io.axi.addr
3535
if2id.io.instIn.data := pcUnit.io.instDataOut
3636
if2id.io.ifFlushIn := ctrlUnit.io.flushIfOut
37-
3837
// id
3938
idUnit.io.inst <> if2id.io.instOut
4039
id2ex.io.instIn <> if2id.io.instOut
4140
ex2ma.io.instIn <> id2ex.io.instOut
4241
maUnit.io.instIn <> ex2ma.io.instOut
4342
ma2wb.io.instIn <> maUnit.io.instOut
44-
43+
//
4544
idUnit.io.id2regfile <> regFileUnit.io.id2regfile
46-
4745
// for load correlation
4846
idUnit.io.exuOperTypeIn := id2ex.io.exAluOperTypeOut
4947
idUnit.io.exuWtAddrIn := id2ex.io.exWtAddrOut
50-
5148
// id to ex
5249
id2ex.io.idAluOperTypeIn := idUnit.io.exuOperTypeOut
5350
id2ex.io.idRsValAIn := idUnit.io.rsValAOut
5451
id2ex.io.idRsValBIn := idUnit.io.rsValBOut
5552
id2ex.io.idWtEnaIn := idUnit.io.wtEnaOut
5653
id2ex.io.idWtAddrIn := idUnit.io.wtAddrOut
5754
id2ex.io.lsuFunc3MSBIn := idUnit.io.lsuFunc3MSBOut
58-
id2ex.io.lsuWtEnaIn := idUnit.io.lsuWtEnaOut
5955
id2ex.io.ifFlushIn := ctrlUnit.io.flushIdOut
6056
// ex
6157
execUnit.io.offsetIn := idUnit.io.exuOffsetOut // important!!!
@@ -68,22 +64,14 @@ class TreeCoreL2() extends Module with AXI4Config with InstConfig {
6864
ex2ma.io.wtIn.addr := id2ex.io.exWtAddrOut
6965
ex2ma.io.wtIn.data := execUnit.io.wtDataOut
7066

71-
ex2ma.io.lsuFunc3MSBIn := id2ex.io.lsuFunc3MSBOut
72-
ex2ma.io.lsuWtEnaIn := id2ex.io.lsuWtEnaOut
73-
ex2ma.io.lsuOperTypeIn := execUnit.io.exuOperTypeIn
74-
ex2ma.io.lsuValAIn := execUnit.io.rsValAIn
75-
ex2ma.io.lsuValBIn := execUnit.io.rsValBIn
76-
ex2ma.io.lsuOffsetIn := RegNext(execUnit.io.offsetIn) // important!!
77-
67+
ex2ma.io.lsInstIn.func3MSB := id2ex.io.lsuFunc3MSBOut
68+
ex2ma.io.lsInstIn.operType := execUnit.io.exuOperTypeIn
69+
ex2ma.io.lsInstIn.valA := execUnit.io.rsValAIn
70+
ex2ma.io.lsInstIn.valB := execUnit.io.rsValBIn
71+
ex2ma.io.lsInstIn.offset := RegNext(execUnit.io.offsetIn) // important!!
7872
// ma
79-
maUnit.io.memFunc3MSBIn := ex2ma.io.lsuFunc3MSBOut
80-
maUnit.io.memOperTypeIn := ex2ma.io.lsuOperTypeOut
81-
maUnit.io.memValAIn := ex2ma.io.lsuValAOut
82-
maUnit.io.memValBIn := ex2ma.io.lsuValBOut
83-
maUnit.io.memOffsetIn := ex2ma.io.lsuOffsetOut
84-
85-
maUnit.io.wtIn <> ex2ma.io.wtOut
86-
ex2ma.io.lsuWtEnaOut := DontCare
73+
maUnit.io.wtIn <> ex2ma.io.wtOut
74+
maUnit.io.lsInstIn <> ex2ma.io.lsInstOut
8775

8876
// ma to wb
8977
ma2wb.io.wtIn <> maUnit.io.wtOut
@@ -95,26 +83,22 @@ class TreeCoreL2() extends Module with AXI4Config with InstConfig {
9583
regFileUnit.io.wtIn <> ma2wb.io.wtOut
9684

9785
// forward control unit
98-
// forwardUnit.io.exIn <> ex2ma.io.wtIn
9986
forwardUnit.io.exIn.ena := ex2ma.io.wtIn.ena
10087
forwardUnit.io.exIn.addr := ex2ma.io.wtIn.addr
10188
forwardUnit.io.exIn.data := ex2ma.io.wtIn.data
10289

10390
// maDataIn only come from regfile and imm
10491
// maDataOut have right data include load/store inst and alu calc
105-
forwardUnit.io.maIn.ena := ma2wb.io.wtIn.ena
106-
forwardUnit.io.maIn.addr := ma2wb.io.wtIn.addr
107-
forwardUnit.io.maIn.data := ma2wb.io.wtIn.data
108-
92+
forwardUnit.io.maIn <> maUnit.io.wtOut
10993
forwardUnit.io.idRdEnaAIn := idUnit.io.id2regfile.rdA.ena
11094
forwardUnit.io.idRdAddrAIn := idUnit.io.id2regfile.rdA.addr
95+
idUnit.io.fwRsEnaAIn := forwardUnit.io.fwRsEnaAOut
96+
idUnit.io.fwRsValAIn := forwardUnit.io.fwRsValAOut
97+
11198
forwardUnit.io.idRdEnaBIn := idUnit.io.id2regfile.rdB.ena
11299
forwardUnit.io.idRdAddrBIn := idUnit.io.id2regfile.rdB.addr
113-
114-
idUnit.io.fwRsEnaAIn := forwardUnit.io.fwRsEnaAOut
115-
idUnit.io.fwRsValAIn := forwardUnit.io.fwRsValAOut
116-
idUnit.io.fwRsEnaBIn := forwardUnit.io.fwRsEnaBOut
117-
idUnit.io.fwRsValBIn := forwardUnit.io.fwRsValBOut
100+
idUnit.io.fwRsEnaBIn := forwardUnit.io.fwRsEnaBOut
101+
idUnit.io.fwRsValBIn := forwardUnit.io.fwRsValBOut
118102

119103
// branch and load/store control
120104
ctrlUnit.io.excpJumpInfo <> csrUnit.io.excpJumpInfo
@@ -235,10 +219,10 @@ class TreeCoreL2() extends Module with AXI4Config with InstConfig {
235219
// printf(p"[csr]io.debugMstatus = 0x${Hexadecimal(csrUnit.io.debugMstatus)}\n")
236220
// printf(p"[ex]io.wtDataOut = 0x${Hexadecimal(execUnit.io.wtDataOut)}\n")
237221

238-
// printf(p"[ma]io.memOperTypeIn = 0x${Hexadecimal(maUnit.io.memOperTypeIn)}\n")
239-
// printf(p"[ma]io.memValAIn = 0x${Hexadecimal(maUnit.io.memValAIn)}\n")
240-
// printf(p"[ma]io.memValBIn = 0x${Hexadecimal(maUnit.io.memValBIn)}\n")
241-
// printf(p"[ma]io.memOffsetIn = 0x${Hexadecimal(maUnit.io.memOffsetIn)}\n")
222+
// printf(p"[ma]io.lsInstIn.operType = 0x${Hexadecimal(maUnit.io.lsInstIn.operType)}\n")
223+
// printf(p"[ma]io.lsInstIn.valA = 0x${Hexadecimal(maUnit.io.lsInstIn.valA)}\n")
224+
// printf(p"[ma]io.lsInstIn.valB = 0x${Hexadecimal(maUnit.io.lsInstIn.valB)}\n")
225+
// printf(p"[ma]io.lsInstIn.offset = 0x${Hexadecimal(maUnit.io.lsInstIn.offset)}\n")
242226
// printf(p"[ma]io.axi.addr = 0x${Hexadecimal(maUnit.io.axi.addr)}\n")
243227
// printf(p"[ma]io.axi.wdata = 0x${Hexadecimal(maUnit.io.axi.wdata)}\n")
244228
// printf(p"[ma]io.axi.size = 0x${Hexadecimal(maUnit.io.axi.size)}\n")

‎rtl/tc_l2/src/main/scala/core/datapath/EXToMA.scala‎

Lines changed: 26 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -5,43 +5,21 @@ import treecorel2.common.ConstVal._
55

66
class EXToMA extends Module with InstConfig {
77
val io = IO(new Bundle {
8+
val instIn: INSTIO = new INSTIO
9+
val wtIn: TRANSIO = Flipped(new TRANSIO(RegAddrLen, BusWidth)) // from ex
10+
val lsInstIn: LSINSTIO = Flipped(new LSINSTIO) // from id&
811

9-
val wtIn: TRANSIO = Flipped(new TRANSIO(RegAddrLen, BusWidth)) // from ex
10-
val wtOut: TRANSIO = new TRANSIO(RegAddrLen, BusWidth) // to ma
11-
12-
val lsuFunc3MSBIn: UInt = Input(UInt(1.W))
13-
val lsuWtEnaIn: Bool = Input(Bool())
14-
val lsuOperTypeIn: UInt = Input(UInt(InstOperTypeLen.W))
15-
val lsuValAIn: UInt = Input(UInt(BusWidth.W))
16-
val lsuValBIn: UInt = Input(UInt(BusWidth.W))
17-
val lsuOffsetIn: UInt = Input(UInt(BusWidth.W))
18-
val instIn: INSTIO = new INSTIO
19-
20-
// to ma
21-
val lsuFunc3MSBOut: UInt = Output(UInt(1.W))
22-
val lsuWtEnaOut: Bool = Output(Bool())
23-
val lsuOperTypeOut: UInt = Output(UInt(InstOperTypeLen.W))
24-
val lsuValAOut: UInt = Output(UInt(BusWidth.W))
25-
val lsuValBOut: UInt = Output(UInt(BusWidth.W))
26-
val lsuOffsetOut: UInt = Output(UInt(BusWidth.W))
27-
val instOut: INSTIO = Flipped(new INSTIO)
12+
val instOut: INSTIO = Flipped(new INSTIO)
13+
val wtOut: TRANSIO = new TRANSIO(RegAddrLen, BusWidth) // to ma
14+
val lsInstOut: LSINSTIO = new LSINSTIO // to ma
2815
})
2916

30-
//####################
31-
protected val instAddrReg: UInt = RegInit(0.U(BusWidth.W))
32-
protected val instDataReg: UInt = RegInit(0.U(InstWidth.W))
33-
34-
instAddrReg := io.instIn.addr
35-
instDataReg := io.instIn.data
36-
io.instOut.addr := instAddrReg
37-
io.instOut.data := instDataReg
38-
//####################
39-
17+
protected val instAddrReg: UInt = RegInit(0.U(BusWidth.W))
18+
protected val instDataReg: UInt = RegInit(0.U(InstWidth.W))
4019
protected val dataReg: UInt = RegInit(0.U(BusWidth.W))
4120
protected val wtEnaReg: Bool = RegInit(false.B)
4221
protected val wtAddrReg: UInt = RegInit(0.U(RegAddrLen.W))
4322
protected val lsuFunc3MSBReg: UInt = RegInit(0.U(1.W))
44-
protected val lsuWtEnaReg: Bool = RegInit(false.B)
4523
protected val lsuOperTypeReg: UInt = RegInit(0.U(InstOperTypeLen.W))
4624
protected val lsuValAReg: UInt = RegInit(0.U(BusWidth.W))
4725
protected val lsuValBReg: UInt = RegInit(0.U(BusWidth.W))
@@ -50,20 +28,22 @@ class EXToMA extends Module with InstConfig {
5028
dataReg := io.wtIn.data
5129
wtEnaReg := io.wtIn.ena
5230
wtAddrReg := io.wtIn.addr
53-
lsuFunc3MSBReg := io.lsuFunc3MSBIn
54-
lsuWtEnaReg := io.lsuWtEnaIn
55-
lsuOperTypeReg := io.lsuOperTypeIn
56-
lsuValAReg := io.lsuValAIn
57-
lsuValBReg := io.lsuValBIn
58-
lsuOffsetReg := io.lsuOffsetIn
59-
60-
io.wtOut.data := dataReg
61-
io.wtOut.ena := wtEnaReg
62-
io.wtOut.addr := wtAddrReg
63-
io.lsuFunc3MSBOut := lsuFunc3MSBReg
64-
io.lsuWtEnaOut := lsuWtEnaReg
65-
io.lsuOperTypeOut := lsuOperTypeReg
66-
io.lsuValAOut := lsuValAReg
67-
io.lsuValBOut := lsuValBReg
68-
io.lsuOffsetOut := lsuOffsetReg
31+
lsuFunc3MSBReg := io.lsInstIn.func3MSB
32+
lsuOperTypeReg := io.lsInstIn.operType
33+
lsuValAReg := io.lsInstIn.valA
34+
lsuValBReg := io.lsInstIn.valB
35+
lsuOffsetReg := io.lsInstIn.offset
36+
instAddrReg := io.instIn.addr
37+
instDataReg := io.instIn.data
38+
39+
io.wtOut.data := dataReg
40+
io.wtOut.ena := wtEnaReg
41+
io.wtOut.addr := wtAddrReg
42+
io.lsInstOut.func3MSB := lsuFunc3MSBReg
43+
io.lsInstOut.operType := lsuOperTypeReg
44+
io.lsInstOut.valA := lsuValAReg
45+
io.lsInstOut.valB := lsuValBReg
46+
io.lsInstOut.offset := lsuOffsetReg
47+
io.instOut.addr := instAddrReg
48+
io.instOut.data := instDataReg
6949
}

‎rtl/tc_l2/src/main/scala/core/datapath/IDToEX.scala‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ class IDToEX extends Module with InstConfig {
1414
val idWtEnaIn: Bool = Input(Bool())
1515
val idWtAddrIn: UInt = Input(UInt(RegAddrLen.W))
1616
val lsuFunc3MSBIn: UInt = Input(UInt(1.W))
17-
val lsuWtEnaIn: Bool = Input(Bool())
1817
val instIn: INSTIO = new INSTIO
1918

2019
// to ex
@@ -25,7 +24,6 @@ class IDToEX extends Module with InstConfig {
2524
val exWtAddrOut: UInt = Output(UInt(RegAddrLen.W))
2625
// ex2ma
2726
val lsuFunc3MSBOut: UInt = Output(UInt(1.W))
28-
val lsuWtEnaOut: Bool = Output(Bool())
2927
val diffIdSkipInstOut: Bool = Output(Bool())
3028
val instOut: INSTIO = Flipped(new INSTIO)
3129
})
@@ -37,7 +35,6 @@ class IDToEX extends Module with InstConfig {
3735
protected val wtEnaReg: Bool = RegInit(false.B)
3836
protected val wtAddrReg: UInt = RegInit(0.U(RegAddrLen.W))
3937
protected val lsuFunc3MSBReg: UInt = RegInit(0.U(1.W))
40-
protected val lsuWtEnaReg: Bool = RegInit(false.B)
4138

4239
//####################
4340
protected val instAddrReg: UInt = RegInit(0.U(BusWidth.W))
@@ -57,7 +54,6 @@ class IDToEX extends Module with InstConfig {
5754
wtEnaReg := false.B
5855
wtAddrReg := 0.U(RegAddrLen.W)
5956
lsuFunc3MSBReg := 0.U(1.W)
60-
lsuWtEnaReg := false.B
6157
}.otherwise {
6258
diffIdSkipInstReg := false.B
6359
aluOperTypeReg := io.idAluOperTypeIn
@@ -66,7 +62,6 @@ class IDToEX extends Module with InstConfig {
6662
wtEnaReg := io.idWtEnaIn
6763
wtAddrReg := io.idWtAddrIn
6864
lsuFunc3MSBReg := io.lsuFunc3MSBIn
69-
lsuWtEnaReg := io.lsuWtEnaIn
7065
}
7166

7267
io.diffIdSkipInstOut := diffIdSkipInstReg
@@ -76,5 +71,4 @@ class IDToEX extends Module with InstConfig {
7671
io.exWtEnaOut := wtEnaReg
7772
io.exWtAddrOut := wtAddrReg
7873
io.lsuFunc3MSBOut := lsuFunc3MSBReg
79-
io.lsuWtEnaOut := lsuWtEnaReg
8074
}

‎rtl/tc_l2/src/main/scala/core/datapath/MAToWB.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@ class MAToWB extends Module with InstConfig {
88
val wtIn: TRANSIO = Flipped(new TRANSIO(RegAddrLen, BusWidth)) // from ma
99
val wtOut: TRANSIO = new TRANSIO(RegAddrLen, BusWidth) // to wb
1010

11-
val ifValidIn: Bool = Input(Bool())
1211
val instIn: INSTIO = new INSTIO
12+
val ifValidIn: Bool = Input(Bool())
1313
val ifMemInstCommitIn: Bool = Input(Bool())
1414
// from clint
1515
val clintWt: TRANSIO = Flipped(new TRANSIO(BusWidth, BusWidth))
@@ -18,8 +18,8 @@ class MAToWB extends Module with InstConfig {
1818
val memIntrEnterFlag: Bool = Input(Bool())
1919

2020
// to difftest
21-
val diffMaSkipInstOut: Bool = Output(Bool())
2221
val instOut: INSTIO = Flipped(new INSTIO)
22+
val diffMaSkipInstOut: Bool = Output(Bool())
2323
val ifMemInstCommitOut: Bool = Output(Bool())
2424
})
2525

‎rtl/tc_l2/src/main/scala/core/exec/ALU.scala‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,6 @@ class ALU extends Module with InstConfig {
1313
val rsValBIn: UInt = Input(UInt(BusWidth.W))
1414
// from csr
1515
val csrRdDataIn: UInt = Input(UInt(BusWidth.W))
16-
1716
// to ex2ma
1817
val wtDataOut: UInt = Output(UInt(BusWidth.W))
1918
// to csr

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