Pull request #38: Update to latest clock settings.

Merge in MCU16CE/dspic33-dsc-bootloader-code-examples from ~C12109/dspic33-dsc-bootloader-code-examples:feature/MCU16GITHUB-958-update-to-new-clock-speed-for-bootloader to feature/MCU16GITHUB-842-add-the-icsp-inhibit-feature

* commit '0ecf88a8843466e0634deb442892143836a0198e':
  Update to latest clock settings.

Author: davidflowers

secure_boot_and_secure_firmware_upgrade_over_canfd/icsp_inhibit.X/icsp_inhibit.mc3

@@ -47,7 +47,7 @@
   @brief    This macro is used to read the System clock (FOSC) Frequency configured in 
             the MCC Melody User Interface
 */
-#define CLOCK_SystemFrequencyGet()        (8000000UL)
+#define CLOCK_SystemFrequencyGet()        (200000000UL)
 
 /** 
   @ingroup  clockdriver

secure_boot_and_secure_firmware_upgrade_over_canfd/icsp_inhibit.X/mcc_generated_files/system/clock.h

@@ -44,21 +44,25 @@ void CLOCK_Initialize(void)
 {
     /*  
        Input frequency                               :  8.00 MHz
-       Clock source                                  :  FRC Oscillator
-       System frequency (Fosc)                       :  8.00 MHz
-       Clock switching enabled                       :  false
+       Clock source                                  :  External Oscillator with PLL
+       System frequency (Fosc)                       :  200.00 MHz [(8.00 MHz / 1) * 50 / 1 / 2 = 200.00 MHz]
+       PLL VCO frequency (Fvco)                      :  400.00 MHz [(8.00 MHz / 1) * 50 = 400.00 MHz]
+       PLL output frequency (Fpllo)                  :  400.00 MHz [(8.00 MHz / 1) * 50 / 1 = 400.00 MHz]
+       PLL VCO divider frequency (Fvcodiv)           :  100.00 MHz [400.00 MHz / 4 = 100.00 MHz]
+       Clock switching enabled                       :  true
+       Clock source when device boots                :  FRC Oscillator
        Auxiliary clock source                        :  FRC Oscillator
        Auxiliary clock input frequency               :  8.00 MHz
        Auxiliary clock PLL output frequency (AFpllo) :  8.00 MHz
     */
     // RCDIV FRC/1; PLLPRE 1:1; DOZE 1:8; DOZEN disabled; ROI disabled; 
     CLKDIV = 0x3001;
-    // PLLDIV 150; 
-    PLLFBD = 0x96;
+    // PLLDIV 50; 
+    PLLFBD = 0x32;
     // TUN Center frequency; 
     OSCTUN = 0x0;
-    // PLLPOST 1:4; VCODIV FVCO/4; POST2DIV 1:1; 
-    PLLDIV = 0x41;
+    // PLLPOST 1:1; VCODIV FVCO/4; POST2DIV 1:1; 
+    PLLDIV = 0x11;
     // ENAPLL disabled; FRCSEL FRC Oscillator; APLLPRE 1:1; 
     ACLKCON1 = 0x101;
     // APLLFBDIV 150; 
@@ -91,9 +95,12 @@ void CLOCK_Initialize(void)
     PMD7 = 0x0;
     // DMTMD enabled; CLC3MD enabled; OPAMPMD enabled; BIASMD enabled; CLC4MD enabled; SENT1MD enabled; CLC1MD enabled; CLC2MD enabled; SENT2MD enabled; 
     PMD8 = 0x0;
-    // CF no clock failure; NOSC FRC; CLKLOCK unlocked; OSWEN Switch is Complete; 
-    __builtin_write_OSCCONH((uint8_t) (0x00));
-    __builtin_write_OSCCONL((uint8_t) (0x00));
+    // CF no clock failure; NOSC PRIPLL; CLKLOCK unlocked; OSWEN Switch is Complete; 
+    __builtin_write_OSCCONH((uint8_t) (0x03));
+    __builtin_write_OSCCONL((uint8_t) (0x01));
+    // Wait for Clock switch to occur
+    while (OSCCONbits.OSWEN != 0);
+    while (OSCCONbits.LOCK != 1);
 }
 
 bool CLOCK_AuxPllLockStatusGet(void)

secure_boot_and_secure_firmware_upgrade_over_canfd/icsp_inhibit.X/mcc_generated_files/system/src/clock.c

@@ -55,9 +55,9 @@
 #pragma config IESO = OFF    //Two-speed Oscillator Start-up Enable bit->Start up with user-selected oscillator source
 
 // FOSC
-#pragma config POSCMD = NONE    //Primary Oscillator Mode Select bits->Primary Oscillator disabled
+#pragma config POSCMD = EC    //Primary Oscillator Mode Select bits->EC (External Clock) Mode
 #pragma config OSCIOFNC = ON    //OSC2 Pin Function bit->OSC2 is general purpose digital I/O pin
-#pragma config FCKSM = CSDCMD    //Clock Switching Mode bits->Both Clock switching and Fail-safe Clock Monitor are disabled
+#pragma config FCKSM = CSECMD    //Clock Switching Mode bits->Clock switching is enabled,Fail-safe Clock Monitor is disabled
 #pragma config PLLKEN = ON    //PLL Lock Status Control->PLL lock signal will be used to disable PLL clock output if lock is lost
 #pragma config XTCFG = G3    //XT Config->24-32 MHz crystals
 #pragma config XTBST = ENABLE    //XT Boost->Boost the kick-start

secure_boot_and_secure_firmware_upgrade_over_canfd/icsp_inhibit.X/mcc_generated_files/system/src/config_bits.c

@@ -98,7 +98,7 @@ void PINS_Initialize(void)
      * Setting the Analog/Digital Configuration SFR(s)
      ***************************************************************************/
     ANSELA = 0x001F;
-    ANSELB = 0x009F;
+    ANSELB = 0x009E;
     ANSELC = 0x00CF;
     ANSELD = 0x2C00;
     ANSELE = 0x000F;

secure_boot_and_secure_firmware_upgrade_over_canfd/icsp_inhibit.X/mcc_generated_files/system/src/pins.c

@@ -43,16 +43,16 @@
 #include "../uart1.h"
 
 // Section: Macro Definitions
-#define UART1_CLOCK 4000000U
+#define UART1_CLOCK 100000000U
 #define UART1_BAUD_TO_BRG_WITH_FRACTIONAL(x) (UART1_CLOCK/(x))
 #define UART1_BAUD_TO_BRG_WITH_BRGH_1(x) (UART1_CLOCK/(4U*(x))-1U)
 #define UART1_BAUD_TO_BRG_WITH_BRGH_0(x) (UART1_CLOCK/(16U*(x))-1U)
 #define UART1_BRG_TO_BAUD_WITH_FRACTIONAL(x) (UART1_CLOCK/(x))
 #define UART1_BRG_TO_BAUD_WITH_BRGH_1(x) (UART1_CLOCK/(4U*((x)+1U)))
 #define UART1_BRG_TO_BAUD_WITH_BRGH_0(x) (UART1_CLOCK/(16U*((x)+1U)))
 
-#define UART1_MIN_ACHIEVABLE_BAUD_WITH_FRACTIONAL 4U
-#define UART1_MIN_ACHIEVABLE_BAUD_WITH_BRGH_1 1U
+#define UART1_MIN_ACHIEVABLE_BAUD_WITH_FRACTIONAL 95U
+#define UART1_MIN_ACHIEVABLE_BAUD_WITH_BRGH_1 24U
 
 // Section: Driver Interface
 
@@ -113,8 +113,8 @@ void UART1_Initialize(void)
     U1STA = 0x80;
     // URXISEL ; UTXBE ; UTXISEL ; URXBE ; STPMD ; TXWRE ; 
     U1STAH = 0x2E;
-    // BaudRate 9592.33; Frequency 4000000 Hz; BRG 417; 
-    U1BRG = 0x1A1;
+    // BaudRate 9599.69; Frequency 100000000 Hz; BRG 10417; 
+    U1BRG = 0x28B1;
     // BRG 0; 
     U1BRGH = 0x0;
 
@@ -256,12 +256,18 @@ void UART1_BaudRateSet(uint32_t baudRate)
         U1MODEbits.BRGH = 0;
         brgValue = UART1_BAUD_TO_BRG_WITH_FRACTIONAL(baudRate);
     }
-    else
+    else if(baudRate >= UART1_MIN_ACHIEVABLE_BAUD_WITH_BRGH_1)
     {
         U1MODEHbits.BCLKMOD = 0;
         U1MODEbits.BRGH = 1;
         brgValue = UART1_BAUD_TO_BRG_WITH_BRGH_1(baudRate);
     }
+    else
+    {
+        U1MODEHbits.BCLKMOD = 0;
+        U1MODEbits.BRGH = 0;
+        brgValue = UART1_BAUD_TO_BRG_WITH_BRGH_0(baudRate);
+    }
     U1BRG = brgValue & 0xFFFFU;
     U1BRGH = (brgValue >>16U) & 0x000FU;
 }