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Pull request #87: Bugfix/CC16BOOT-8480 update dspic33a bootloader and firmware upgrade demo
Merge in MCU16CE/dspic33-dsc-bootloader-code-examples from ~C74569/dspic33-dsc-bootloader-code-examples:bugfix/CC16BOOT-8480-update-dspic33a_bootloader_and_firmware_upgrade_demo to develop * commit 'ad7cf89d9e4f229d1bd1b5df9b26ca5db7a4da4e': Update flash protection project Update app project Update boot project
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dspic33a_bootloader_and_firmware_upgrade_demo/app.X/app.mc3

Lines changed: 5 additions & 5 deletions
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dspic33a_bootloader_and_firmware_upgrade_demo/app.X/mcc_generated_files/system/clock.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
*
88
* @brief Clock configurator driver for System and Peripheral Clock using dsPIC MCUs.
99
*
10-
* @version PLIB Version 1.1.0
10+
* @skipline @version PLIB Version 1.1.2
1111
*
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* @skipline Device : dsPIC33AK128MC106
1313
*/

dspic33a_bootloader_and_firmware_upgrade_demo/app.X/mcc_generated_files/system/clock_types.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
*
88
* @brief This is the generated driver types header file for the CLOCK driver
99
*
10-
* @version PLIB Version 1.1.0
10+
* @skipline @version PLIB Version 1.1.2
1111
*
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* @skipline Device : dsPIC33AK128MC106
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*/
@@ -43,9 +43,9 @@
4343
*/
4444
enum CLOCK_GENERATOR
4545
{
46-
CLOCK_GENERATOR_1, /**< Clock Generator 1 */
47-
CLOCK_GENERATOR_2, /**< Clock Generator 2 */
48-
CLOCK_GENERATOR_3, /**< Clock Generator 3 */
46+
CLOCK_GENERATOR_1 = 1, /**< Clock Generator 1 */
47+
CLOCK_GENERATOR_2 = 2, /**< Clock Generator 2 */
48+
CLOCK_GENERATOR_3 = 3, /**< Clock Generator 3 */
4949

5050
CLOCK_SYSTEM = 1, /**< Clock for System */
5151
CLOCK_FRC = 2, /**< Clock for FRC */

dspic33a_bootloader_and_firmware_upgrade_demo/app.X/mcc_generated_files/system/src/clock.c

Lines changed: 46 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
*
99
* @brief This is the generated source file for CLOCK driver
1010
*
11-
* @version PLIB Version 1.1.0
11+
* @version PLIB Version 1.1.2
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*
1313
* @skipline Device : dsPIC33AK128MC106
1414
*/
@@ -42,8 +42,12 @@
4242
#include "../clock.h"
4343
#include "../clock_types.h"
4444

45+
#define PLL1FOUT_SOURCE 0x5U
46+
#define PLL2VCODIV_SOURCE 0x8U
47+
4548
// Section: Static Variables
4649

50+
4751
void CLOCK_Initialize(void)
4852
{
4953
/*
@@ -57,65 +61,83 @@ void CLOCK_Initialize(void)
5761
PLL 1 VCO Out frequency : 200 MHz
5862
5963
*/
60-
61-
/* Always switch to FRC before making clock changes. */
62-
CLK1CONbits.NOSC = 1; // FRC_CLK
63-
CLK1CONbits.OSWEN = 1;
64-
while(CLK1CONbits.OSWEN){}
64+
65+
66+
//If CLK GEN 1 (system clock) is using a PLL, switch to FRC to avoid risk of over-clocking the CPU while changing PLL settings
67+
if((CLK1CONbits.COSC >= PLL1FOUT_SOURCE) && (CLK1CONbits.COSC <= PLL2VCODIV_SOURCE))
68+
{
69+
CLK1CONbits.NOSC = 1U; //FRC as source
70+
CLK1CONbits.OSWEN = 1U;
71+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
72+
while(CLK1CONbits.OSWEN == 1U){};
73+
#endif
74+
}
6575

6676
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL disabled; EXTCFEN disabled; FOUTSWEN disabled; RIS disabled; PLLSWEN disabled;
67-
PLL1CON = 0x000129100UL;
77+
PLL1CON = 0x9100UL;
6878
// POSTDIV2 2x divide; POSTDIV1 4x divide; PLLFBDIV 200; PLLPRE 1;
6979
PLL1DIV = 0x100C822UL;
7080
//Enable PLL Input and Feedback Divider update
7181
PLL1CONbits.PLLSWEN = 1U;
82+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
7283
while (PLL1CONbits.PLLSWEN == 1){};
84+
#endif
7385
PLL1CONbits.FOUTSWEN = 1U;
86+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
7487
while (PLL1CONbits.FOUTSWEN == 1U){};
75-
88+
#endif
7689
//enable clock switching
7790
PLL1CONbits.OSWEN = 1U;
91+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
7892
//wait for switching
7993
while(PLL1CONbits.OSWEN == 1U){};
8094
//wait for clock to be ready
8195
while(OSCCTRLbits.PLL1RDY == 0U){};
96+
#endif
8297

8398
//Configure VCO Divider
8499
// INTDIV 4;
85100
VCO1DIV = 0x40000UL;
86101
//enable PLL VCO divider
87-
PLL1CONbits.DIVSWEN = 1U;
102+
PLL1CONbits.DIVSWEN = 1U;
103+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
88104
//wait for setup complete
89105
while(PLL1CONbits.DIVSWEN == 1U){};
106+
#endif
107+
//Clearing ON shuts down oscillator when no downstream clkgen or peripheral is requesting the clock
108+
PLL1CONbits.ON = 0U;
90109

91-
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
92-
CLK1CON = 0x000129500UL;
110+
// NOSC PLL1 Out output; OE enabled; SIDL disabled; ON enabled; BOSC Backup FRC Oscillator; FSCMEN enabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
111+
CLK1CON = 0x129500UL;
93112
// FRACDIV 0; INTDIV 0;
94113
CLK1DIV = 0x0UL;
95114
//enable clock switching
96-
CLK1CONbits.OSWEN = 1U;
115+
CLK1CONbits.OSWEN = 1U;
116+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
97117
//wait for clock switching complete
98118
while(CLK1CONbits.OSWEN == 1U){};
119+
#endif
99120

100-
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
101-
CLK2CON = 0x000129101UL;
121+
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Backup FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
122+
CLK2CON = 0x29101UL;
102123
//enable clock switching
103-
CLK2CONbits.OSWEN = 1U;
124+
CLK2CONbits.OSWEN = 1U;
125+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
104126
//wait for clock switching complete
105127
while(CLK2CONbits.OSWEN == 1U){};
128+
#endif
106129

107-
// NOSC Backup FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
108-
CLK3CON = 0x000129202UL;
130+
// NOSC Backup FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
131+
CLK3CON = 0x19202UL;
109132
//enable clock switching
110-
CLK3CONbits.OSWEN = 1U;
133+
CLK3CONbits.OSWEN = 1U;
134+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
111135
//wait for clock switching complete
112-
while(CLK3CONbits.OSWEN == 1U){};
136+
while(CLK3CONbits.OSWEN == 1U){};
137+
#endif
138+
139+
113140

114-
// Allow clocks to disable unless required by a peripheral
115-
CLK1CONbits.ON = 0;
116-
CLK2CONbits.ON = 0;
117-
CLK3CONbits.ON = 0;
118-
PLL1CONbits.ON = 0;
119141
}
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