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Update boot project
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5 files changed

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-340
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5 files changed

+366
-340
lines changed

dspic33a_bootloader_and_firmware_upgrade_demo/boot.X/boot.mc3

Lines changed: 5 additions & 5 deletions
Large diffs are not rendered by default.

dspic33a_bootloader_and_firmware_upgrade_demo/boot.X/mcc_generated_files/system/clock.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
*
88
* @brief Clock configurator driver for System and Peripheral Clock using dsPIC MCUs.
99
*
10-
* @version PLIB Version 1.1.0
10+
* @skipline @version PLIB Version 1.1.2
1111
*
1212
* @skipline Device : dsPIC33AK128MC106
1313
*/

dspic33a_bootloader_and_firmware_upgrade_demo/boot.X/mcc_generated_files/system/clock_types.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
*
88
* @brief This is the generated driver types header file for the CLOCK driver
99
*
10-
* @version PLIB Version 1.1.0
10+
* @skipline @version PLIB Version 1.1.2
1111
*
1212
* @skipline Device : dsPIC33AK128MC106
1313
*/
@@ -43,9 +43,9 @@
4343
*/
4444
enum CLOCK_GENERATOR
4545
{
46-
CLOCK_GENERATOR_1, /**< Clock Generator 1 */
47-
CLOCK_GENERATOR_2, /**< Clock Generator 2 */
48-
CLOCK_GENERATOR_3, /**< Clock Generator 3 */
46+
CLOCK_GENERATOR_1 = 1, /**< Clock Generator 1 */
47+
CLOCK_GENERATOR_2 = 2, /**< Clock Generator 2 */
48+
CLOCK_GENERATOR_3 = 3, /**< Clock Generator 3 */
4949

5050
CLOCK_SYSTEM = 1, /**< Clock for System */
5151
CLOCK_FRC = 2, /**< Clock for FRC */

dspic33a_bootloader_and_firmware_upgrade_demo/boot.X/mcc_generated_files/system/src/clock.c

Lines changed: 49 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
*
99
* @brief This is the generated source file for CLOCK driver
1010
*
11-
* @version PLIB Version 1.1.0
11+
* @version PLIB Version 1.1.2
1212
*
1313
* @skipline Device : dsPIC33AK128MC106
1414
*/
@@ -42,6 +42,9 @@
4242
#include "../clock.h"
4343
#include "../clock_types.h"
4444

45+
#define PLL1FOUT_SOURCE 0x5U
46+
#define PLL2VCODIV_SOURCE 0x8U
47+
4548
// Section: Static Variables
4649

4750

@@ -60,63 +63,81 @@ void CLOCK_Initialize(void)
6063
*/
6164

6265

63-
/* Always switch to FRC before making clock changes. */
64-
CLK1CONbits.NOSC = 1; // FRC_CLK
65-
CLK1CONbits.OSWEN = 1;
66-
while(CLK1CONbits.OSWEN){}
66+
//If CLK GEN 1 (system clock) is using a PLL, switch to FRC to avoid risk of over-clocking the CPU while changing PLL settings
67+
if((CLK1CONbits.COSC >= PLL1FOUT_SOURCE) && (CLK1CONbits.COSC <= PLL2VCODIV_SOURCE))
68+
{
69+
CLK1CONbits.NOSC = 1U; //FRC as source
70+
CLK1CONbits.OSWEN = 1U;
71+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
72+
while(CLK1CONbits.OSWEN == 1U){};
73+
#endif
74+
}
6775

6876
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL disabled; EXTCFEN disabled; FOUTSWEN disabled; RIS disabled; PLLSWEN disabled;
69-
PLL1CON = 0x000129100UL;
77+
PLL1CON = 0x9100UL;
7078
// POSTDIV2 2x divide; POSTDIV1 4x divide; PLLFBDIV 200; PLLPRE 1;
7179
PLL1DIV = 0x100C822UL;
7280
//Enable PLL Input and Feedback Divider update
7381
PLL1CONbits.PLLSWEN = 1U;
74-
while (PLL1CONbits.PLLSWEN == 1){}
82+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
83+
while (PLL1CONbits.PLLSWEN == 1){};
84+
#endif
7585
PLL1CONbits.FOUTSWEN = 1U;
76-
while (PLL1CONbits.FOUTSWEN == 1U){}
86+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
87+
while (PLL1CONbits.FOUTSWEN == 1U){};
88+
#endif
7789
//enable clock switching
7890
PLL1CONbits.OSWEN = 1U;
91+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
7992
//wait for switching
8093
while(PLL1CONbits.OSWEN == 1U){};
8194
//wait for clock to be ready
82-
while(OSCCTRLbits.PLL1RDY == 0U){}
95+
while(OSCCTRLbits.PLL1RDY == 0U){};
96+
#endif
8397

8498
//Configure VCO Divider
8599
// INTDIV 4;
86100
VCO1DIV = 0x40000UL;
87101
//enable PLL VCO divider
88-
PLL1CONbits.DIVSWEN = 1U;
102+
PLL1CONbits.DIVSWEN = 1U;
103+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
89104
//wait for setup complete
90-
while(PLL1CONbits.DIVSWEN == 1U){}
105+
while(PLL1CONbits.DIVSWEN == 1U){};
106+
#endif
107+
//Clearing ON shuts down oscillator when no downstream clkgen or peripheral is requesting the clock
108+
PLL1CONbits.ON = 0U;
91109

92-
// NOSC PLL1 Out output; OE enabled; SIDL disabled; ON enabled; BOSC FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
93-
CLK1CON = 0x000129500UL;
110+
// NOSC PLL1 Out output; OE enabled; SIDL disabled; ON enabled; BOSC Backup FRC Oscillator; FSCMEN enabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
111+
CLK1CON = 0x129500UL;
94112
// FRACDIV 0; INTDIV 0;
95113
CLK1DIV = 0x0UL;
96114
//enable clock switching
97-
CLK1CONbits.OSWEN = 1U;
115+
CLK1CONbits.OSWEN = 1U;
116+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
98117
//wait for clock switching complete
99-
while(CLK1CONbits.OSWEN == 1U){}
118+
while(CLK1CONbits.OSWEN == 1U){};
119+
#endif
100120

101-
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
102-
CLK2CON = 0x000129101UL;
121+
// NOSC FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Backup FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
122+
CLK2CON = 0x29101UL;
103123
//enable clock switching
104-
CLK2CONbits.OSWEN = 1U;
124+
CLK2CONbits.OSWEN = 1U;
125+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
105126
//wait for clock switching complete
106-
while(CLK2CONbits.OSWEN == 1U){}
127+
while(CLK2CONbits.OSWEN == 1U){};
128+
#endif
107129

108-
// NOSC Backup FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC Serial Test Mode clock (PGC); FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
109-
CLK3CON = 0x000129202UL;
130+
// NOSC Backup FRC Oscillator; OE enabled; SIDL disabled; ON enabled; BOSC FRC Oscillator; FSCMEN disabled; DIVSWEN disabled; OSWEN disabled; EXTCFSEL External clock fail detection module #1; EXTCFEN disabled; RIS disabled;
131+
CLK3CON = 0x19202UL;
110132
//enable clock switching
111-
CLK3CONbits.OSWEN = 1U;
133+
CLK3CONbits.OSWEN = 1U;
134+
#ifndef __MPLAB_DEBUGGER_SIMULATOR
112135
//wait for clock switching complete
113-
while(CLK3CONbits.OSWEN == 1U){}
136+
while(CLK3CONbits.OSWEN == 1U){};
137+
#endif
138+
139+
114140

115-
// Allow clocks to disable unless required by a peripheral
116-
CLK1CONbits.ON = 0;
117-
CLK2CONbits.ON = 0;
118-
CLK3CONbits.ON = 0;
119-
PLL1CONbits.ON = 0;
120141
}
121142

122143

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