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3 | 3 | * Copyright (c) 2020 Arm Limited |
4 | 4 | * Copyright (c) 2021-2023 Nordic Semiconductor ASA |
5 | 5 | * Copyright (c) 2025 Aerlync Labs Inc. |
| 6 | + * Copyright (c) 2025 Siemens Mobility GmbH |
6 | 7 | * |
7 | 8 | * Licensed under the Apache License, Version 2.0 (the "License"); |
8 | 9 | * you may not use this file except in compliance with the License. |
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32 | 33 | #include <zephyr/cache.h> |
33 | 34 | #endif |
34 | 35 |
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35 | | -#if defined(CONFIG_ARM) |
| 36 | +#if defined(CONFIG_CPU_CORTEX_M) |
36 | 37 | #include <cmsis_core.h> |
37 | 38 | #endif |
38 | 39 |
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@@ -142,8 +143,19 @@ extern void *_vector_table_pointer; |
142 | 143 | #endif |
143 | 144 |
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144 | 145 | struct arm_vector_table { |
| 146 | +#ifdef CONFIG_CPU_CORTEX_M |
145 | 147 | uint32_t msp; |
146 | 148 | uint32_t reset; |
| 149 | +#else |
| 150 | + uint32_t reset; |
| 151 | + uint32_t undef_instruction; |
| 152 | + uint32_t svc; |
| 153 | + uint32_t abort_prefetch; |
| 154 | + uint32_t abort_data; |
| 155 | + uint32_t reserved; |
| 156 | + uint32_t irq; |
| 157 | + uint32_t fiq; |
| 158 | +#endif |
147 | 159 | }; |
148 | 160 |
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149 | 161 | static void do_boot(struct boot_rsp *rsp) |
@@ -226,7 +238,10 @@ static void do_boot(struct boot_rsp *rsp) |
226 | 238 | #endif |
227 | 239 | #endif /* CONFIG_BOOT_INTR_VEC_RELOC */ |
228 | 240 |
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| 241 | +#ifdef CONFIG_CPU_CORTEX_M |
229 | 242 | __set_MSP(vt->msp); |
| 243 | +#endif |
| 244 | + |
230 | 245 | #if CONFIG_MCUBOOT_CLEANUP_ARM_CORE |
231 | 246 | __set_CONTROL(0x00); /* application will configures core on its own */ |
232 | 247 | __ISB(); |
@@ -260,7 +275,18 @@ static void do_boot(struct boot_rsp *rsp) |
260 | 275 | : "r0", "r1", "r2", "r3", "memory" |
261 | 276 | ); |
262 | 277 | #else |
| 278 | + |
| 279 | +#ifdef CONFIG_CPU_CORTEX_M |
263 | 280 | ((void (*)(void))vt->reset)(); |
| 281 | +#else |
| 282 | + /* Some ARM CPUs like the Cortex-R5 can run in thumb mode but reset into ARM |
| 283 | + * mode (depending on a CPU signal configurations). To do the switch into ARM |
| 284 | + * mode, if needed, an explicit branch with exchange instruction set |
| 285 | + * instruction is needed |
| 286 | + */ |
| 287 | + __asm__("bx %0\n" : : "r" (&vt->reset)); |
| 288 | +#endif |
| 289 | + |
264 | 290 | #endif |
265 | 291 | } |
266 | 292 |
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