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the-snowwhitethe-snowwhite
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Add KR260 board with Vivado 2022.2 running on Ubuntu on Xilinx 22.04 LTS
https://ubuntu.com/download/amd-xilinx Signed-off-by: the-snowwhite <producer@holotronic.dk>
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lines changed

‎HW/VivadoProjects/make_bitfile.sh‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ sed -e "s|%PIN_NAME%|$PIN_NAME|" \
4949
"$IP_DIR"/src/hostmot2_ip_wrap.vhd
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5151
PRJ_FILE="$PRJ_DIR_CREATED"/"$PRJ_NAME".tcl
52-
BIT_FILE="$PRJ_NAME".bit
52+
BIT_FILE="$PRJ_NAME".bit.bin
5353

5454
# Update the project creation script from the config
5555
sed -e "s|%PRJ_NAME%|$PRJ_NAME|" \
@@ -81,10 +81,16 @@ python genfwid.py "$FWID_NAME" > "$PRJ_DIR_CREATED/firmware_id.mif"
8181
cd ../VivadoProjects
8282

8383
# Run the tcl script to build the project and generate the bitfile
84-
/tools/Xilinx/Vivado/2019.1/bin/vivado -mode batch -source "$PRJ_FILE"
84+
if [[ "$1" == *"kr260"* ]]; then
85+
/tools/Xilinx/Vivado/2022.2/bin/vivado -mode batch -source "$PRJ_FILE"
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else
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/tools/Xilinx/Vivado/2019.1/bin/vivado -mode batch -source "$PRJ_FILE"
88+
fi
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8590

8691
# bootgen: skip mpsoc projects
87-
if test "${1#*"ultra96"}" = "$1" && test "${1#*"fz3"}" = "$1" && test "${1#*"ultramyir"}" = "$1"; then
92+
#if test "${1#*"ultra96"}" = "$1" && test "${1#*"fz3"}" = "$1" && test "${1#*"ultramyir"}" = "$1" && test "${1#*"kr260"}" = "$1"; then
93+
if [[ "$1" == *"microzed"* ]] || [[ "$1" == *"zturn"* ]]; then
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8995
# Update the bif file for bootgen
9096
# component file1 needs the pin file path

‎HW/VivadoProjects/make_mpsoc_boot.sh‎

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,16 +21,25 @@ case $1 in
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*"ultra96"*)
2222
cd /work/HW/VivadoProjects/avnet/ultra96
2323
BOARD_PART="xczu3eg"
24+
rev="2019.1"
2425
;;
2526

2627
*"fz3"*)
2728
cd /work/HW/VivadoProjects/myirtech/fz3
2829
BOARD_PART="xczu3eg"
30+
rev="2019.1"
2931
;;
3032

3133
*"ultramyir"*)
3234
cd /work/HW/VivadoProjects/myirtech/ultramyir
3335
BOARD_PART="xczu3eg"
36+
rev="2019.1"
37+
;;
38+
39+
*"kr260"*)
40+
cd /work/HW/VivadoProjects/xilinx/kr260
41+
BOARD_PART="xck26"
42+
rev="2022.2"
3443
;;
3544

3645
*)
@@ -39,12 +48,14 @@ case $1 in
3948
;;
4049
esac
4150

51+
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4253
# Delete any old project artifacts folder
43-
PRJ_DIR_CREATED=./"$1"-mk-2019.1
54+
PRJ_DIR_CREATED=./"$1"-mk-"$rev"
4455
[ -d "$PRJ_DIR_CREATED" ] && rm -rf "$PRJ_DIR_CREATED"
4556

46-
petalinux-create -t project -s "$1"-mk-2019.1.bsp
47-
cd "$1"-mk-2019.1
57+
petalinux-create -t project -s "$1"-mk-"$rev".bsp
58+
cd "$1"-mk-"$rev"
4859
time petalinux-config --get-hw-description=../"$1"_"$BOARD_PART"_created/"$1"_"$BOARD_PART".sdk --silentconfig
4960
time petalinux-build
5061
petalinux-package --boot --fsbl images/linux/zynqmp_fsbl.elf --u-boot=images/linux/u-boot.elf --pmufw --atf --fpga images/linux/system.bit --force

‎HW/VivadoProjects/xilinx/kr260/const/PIN_KR260_36.vhd‎

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library IEEE;
2+
use IEEE.std_logic_1164.all; -- defines std_logic types
3+
use IEEE.STD_LOGIC_ARITH.ALL;
4+
use IEEE.STD_LOGIC_UNSIGNED.ALL;
5+
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
7+
-- http://www.mesanet.com
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--
9+
-- Ported to MYIR ZTURN IO Carrier board:
10+
-- Copyright (C) 2016, Devin Hughes, JD Squared
11+
-- http://www.jd2.com
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--
13+
-- This program is is licensed under a disjunctive dual license giving you
14+
-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
16+
--
17+
-- * GNU General Public License (GPL), version 2.0 or later
18+
-- * 3-clause BSD License
19+
--
20+
--
21+
-- The GNU GPL License:
22+
--
23+
-- This program is free software; you can redistribute it and/or modify
24+
-- it under the terms of the GNU General Public License as published by
25+
-- the Free Software Foundation; either version 2 of the License, or
26+
-- (at your option) any later version.
27+
--
28+
-- This program is distributed in the hope that it will be useful,
29+
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
30+
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31+
-- GNU General Public License for more details.
32+
--
33+
-- You should have received a copy of the GNU General Public License
34+
-- along with this program; if not, write to the Free Software
35+
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36+
--
37+
--
38+
-- The 3-clause BSD License:
39+
--
40+
-- Redistribution and use in source and binary forms, with or without
41+
-- modification, are permitted provided that the following conditions
42+
-- are met:
43+
--
44+
-- * Redistributions of source code must retain the above copyright
45+
-- notice, this list of conditions and the following disclaimer.
46+
--
47+
-- * Redistributions in binary form must reproduce the above
48+
-- copyright notice, this list of conditions and the following
49+
-- disclaimer in the documentation and/or other materials
50+
-- provided with the distribution.
51+
--
52+
-- * Neither the name of Mesa Electronics nor the names of its
53+
-- contributors may be used to endorse or promote products
54+
-- derived from this software without specific prior written
55+
-- permission.
56+
--
57+
--
58+
-- Disclaimer:
59+
--
60+
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
62+
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
66+
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
67+
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
68+
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69+
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
70+
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
71+
-- POSSIBILITY OF SUCH DAMAGE.
72+
--
73+
74+
use work.IDROMConst.all;
75+
76+
package PIN_KR260_36 is
77+
constant ModuleID : ModuleIDType :=(
78+
(HM2DPLLTag, x"00", ClockLowTag, x"04", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
79+
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
80+
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
81+
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
82+
(FWIDTag, x"00", ClockLowTag, x"01", FWIDAddr&PadT, FWIDNumRegs, x"00", FWIDMPBitMask),
83+
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
84+
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
85+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
86+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
87+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
89+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
90+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
91+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
92+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
94+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
95+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
96+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
97+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
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(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
100+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
101+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
102+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
103+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
104+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
105+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
106+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
107+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
108+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
109+
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
110+
);
111+
112+
113+
constant PinDesc : PinDescType :=(
114+
-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func HD = 3V3, SD = 1V8
115+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 00 HD_GPIO0_0 J15_11 GPIO
116+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 HD_GPIO0_1 J15_12 GPIO
117+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 02 HD_GPIO0_2 J15_13 GPIO
118+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 HD_GPIO0_3 J15_14 GPIO
119+
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 HD_GPIO0_4 J15_15 A Dir
120+
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 05 HD_GPIO0_5 J15_16 A Step
121+
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 06 HD_GPIO0_6 J15_17 B Dir
122+
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 07 HD_GPIO0_7 J15_18 B Step
123+
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 08 HD_GPIO0_8 J16_21 C Dir
124+
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 HD_GPIO0_9 J16_22 C Step
125+
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 10 HD_GPIO0_10 J16_23 D Dir
126+
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 HD_GPIO0_11 J16_24 D Step
127+
IOPortTag & x"00" & HM2DPLLTag & HM2DPLLRefOutPin, -- I/O 12 HD_GPIO0_12 J16_25 DPLL Ref Output
128+
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 13 HD_GPIO0_14 J16_26 Input 1 (Quad A)
129+
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 14 HD_GPIO0_14 J16_27 Input 2 (Quad B)
130+
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 15 HD_GPIO0_15 J16_28 Input 3 (Quad Idx)
131+
132+
-- Base func sec unit sec func sec pin -- hostmot2 Header Pin Func
133+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 16 HD_GPIO0_16 J16_31 GPIO
134+
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 17 HD_GPIO0_17 J16_32 PWM
135+
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 18 HD_GPIO0_18 J16_33 PWM
136+
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 19 HD_GPIO0_19 J16_34 PWM
137+
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 20 HD_GPIO0_20 J16_35 E Dir
138+
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 HD_GPIO0_21 J16_36 E Step
139+
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 22 HD_GPIO0_22 J16_37 F Dir
140+
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 23 HD_GPIO0_23 J16_38 F Step
141+
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 24 SD_GPIO0_24 J15_21 G Dir
142+
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 25 SD_GPIO0_25 J15_22 G Step
143+
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 26 SD_GPIO0_26 J15_23 H Dir
144+
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 27 SD_GPIO0_27 J15_24 H Step
145+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 SD_GPIO0_28 J15_25 GPIO
146+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 SD_GPIO0_29 J15_26 GPIO
147+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 SD_GPIO0_30 J15_27 GPIO
148+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 SD_GPIO0_31 J15_28 GPIO
149+
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 SD_GPIO0_32 J15_31 GPIO
150+
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 SD_GPIO0_33 J15_32 Input 1 (Quad A)
151+
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 SD_GPIO0_34 J15_33 Input 2 (Quad B)
152+
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 SD_GPIO0_35 J15_34 Input 3 (Quad Idx)
153+
154+
-- Fill remaining 144 pins
155+
emptypin,emptypin,emptypin,emptypin,
156+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
157+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
158+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
159+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
160+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
161+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
162+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
163+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
164+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
165+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
166+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
167+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
168+
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
169+
170+
end package PIN_KR260_36;

‎HW/VivadoProjects/xilinx/kr260/const/kr260_pinmap.xdc‎

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1+
#Fan Speed Enable
2+
set_property PACKAGE_PIN A12 [get_ports {fan_en_b[0]}]
3+
set_property SLEW SLOW [get_ports {fan_en_b[0]}]
4+
set_property DRIVE 4 [get_ports {fan_en_b[0]}]
5+
6+
#######################################################################
7+
# KR260 MESA Hostmot2 Signals
8+
#######################################################################
9+
######################## PMOD 1 Upper ########################
10+
set_property PACKAGE_PIN H12 [get_ports {IOBits[0]}]
11+
set_property PACKAGE_PIN E10 [get_ports {IOBits[1]}]
12+
set_property PACKAGE_PIN D10 [get_ports {IOBits[2]}]
13+
set_property PACKAGE_PIN C11 [get_ports {IOBits[3]}]
14+
15+
######################## PMOD 1 Lower ########################
16+
set_property PACKAGE_PIN B10 [get_ports {IOBits[4]}]
17+
set_property PACKAGE_PIN E12 [get_ports {IOBits[5]}]
18+
set_property PACKAGE_PIN D11 [get_ports {IOBits[6]}]
19+
set_property PACKAGE_PIN B11 [get_ports {IOBits[7]}]
20+
21+
######################## PMOD 2 Upper ########################
22+
set_property PACKAGE_PIN J11 [get_ports {IOBits[8]}]
23+
set_property PACKAGE_PIN J10 [get_ports {IOBits[9]}]
24+
set_property PACKAGE_PIN K13 [get_ports {IOBits[10]}]
25+
set_property PACKAGE_PIN K12 [get_ports {IOBits[11]}]
26+
27+
######################## PMOD 2 Lower ########################
28+
set_property PACKAGE_PIN H11 [get_ports {IOBits[12]}]
29+
set_property PACKAGE_PIN G10 [get_ports {IOBits[13]}]
30+
set_property PACKAGE_PIN F12 [get_ports {IOBits[14]}]
31+
set_property PACKAGE_PIN F11 [get_ports {IOBits[15]}]
32+
33+
######################## PMOD 3 Upper ########################
34+
set_property PACKAGE_PIN AE12 [get_ports {IOBits[16]}]
35+
set_property PACKAGE_PIN AF12 [get_ports {IOBits[17]}]
36+
set_property PACKAGE_PIN AG10 [get_ports {IOBits[18]}]
37+
set_property PACKAGE_PIN AH10 [get_ports {IOBits[19]}]
38+
39+
######################## PMOD 3 Lower ########################
40+
set_property PACKAGE_PIN AF11 [get_ports {IOBits[20]}]
41+
set_property PACKAGE_PIN AG11 [get_ports {IOBits[21]}]
42+
set_property PACKAGE_PIN AH12 [get_ports {IOBits[22]}]
43+
set_property PACKAGE_PIN AH11 [get_ports {IOBits[23]}]
44+
45+
######################## PMOD 4 Upper ########################
46+
set_property PACKAGE_PIN AC12 [get_ports {IOBits[24]}]
47+
set_property PACKAGE_PIN AD12 [get_ports {IOBits[25]}]
48+
set_property PACKAGE_PIN AE10 [get_ports {IOBits[26]}]
49+
set_property PACKAGE_PIN AF10 [get_ports {IOBits[27]}]
50+
51+
######################## PMOD 4 Lower ########################
52+
set_property PACKAGE_PIN AD11 [get_ports {IOBits[28]}]
53+
set_property PACKAGE_PIN AD10 [get_ports {IOBits[29]}]
54+
set_property PACKAGE_PIN AA11 [get_ports {IOBits[30]}]
55+
set_property PACKAGE_PIN AA10 [get_ports {IOBits[31]}]
56+
57+
set_property PACKAGE_PIN AD15 [get_ports {LED[0]}]
58+
set_property PACKAGE_PIN AD14 [get_ports {IOBits[32]}]
59+
set_property PACKAGE_PIN AE15 [get_ports {IOBits[33]}]
60+
set_property PACKAGE_PIN AE14 [get_ports {IOBits[34]}]
61+
set_property PACKAGE_PIN AG14 [get_ports {IOBits[35]}]
62+
set_property PACKAGE_PIN AH14 [get_ports {RATES[0]}]
63+
set_property PACKAGE_PIN AG13 [get_ports {RATES[1]}]
64+
set_property PACKAGE_PIN AH13 [get_ports {RATES[2]}]
65+
66+
# Set the bank voltage for IO Bank 43 to 3.3V
67+
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 43]]
68+
69+
# Set the bank voltage for IO Bank 44 to 3.3V
70+
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 44]]
71+
72+
# Set the bank voltage for IO Bank 45 to 3.3V
73+
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 45]]
74+
75+
# Set the bank voltage for IO Bank 65 to 1.8V
76+
#set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 65]]
77+
78+
# Set the bank voltage for IO Bank 66 to 1.8V
79+
#set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 66]]
80+

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